The Job

LPDDR IP Design Senior Staff Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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Synopsys is seeking a Senior Staff Engineer for their LPDDR PHY IP team in Bengaluru, India. This full-time, on-site role involves leading the design of LPDDR PHY IP from specification to productization, including writing Verilog/SystemVerilog code, conducting simulations, and collaborating with verification, timing, DFT, and power teams.

Ansvarsområden

  • Design and micro-architect LPDDR PHY IP
  • Write Verilog and SystemVerilog code and design specifications
  • Conduct simulation and analysis of designs
  • Work with Verification, Timing, DFT, and Power team members
  • Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues
  • Maintain and improve design automation flow and process
  • Contribute to all phases of DDR PHY IP design from design specification to productization
  • Provide customer support for their SoCs

Krav

  • BS in Electrical Engineering
  • Minimum of 6 years of experience in complex technical development
  • Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
  • Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
  • Excellent communication skills
  • Self-motivated

Önskade kvalifikationer

  • Understanding of memory and memory PHY architecture is a plus

Förmåner

  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement Plans
  • Competitive salaries
#Engineering#Hardware Engineers#semiconductor solutions#chip architecture#circuit design#verification#semiconductor products#LPDDR IP#mixed-signal IP#PHY IP#ASIC Digital Design Engineer#DesignWare LPDDR PHY IP#SoCs#design specification#micro-architecting#Verilog#SystemVerilog#simulation#analysis#Verification#Timing#DFT#Power team#Lint#CDC/RDC#power optimization#front-end design flows#synthesis#timing investigation#closure#cross-domain clocking#memory architecture
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Företag

Synopsys Inc

Publicerade jobb

för 13 timmar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

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