LPDDR IP Design Principle Engineer
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling
I korthet
Synopsys is seeking a Sr. Staff ASIC Digital Design Engineer for their LPDDR PHY IP team in Bengaluru, India. The role involves contributing to all phases of LPDDR PHY IP design, from specification to productization, and requires expertise in Verilog/SystemVerilog, front-end design flows, and optimization techniques.
Ansvarsområden
- Design and micro-architect LPDDR PHY IP.
- Write Verilog and SystemVerilog code and design specifications.
- Conduct simulations and analysis of designs.
- Work with Verification, Timing, DFT, and Power team members.
- Analyze and fix Lint, CDC/RDC, DFT, Timing, and power issues.
- Maintain and improve design automating flow and process.
- Provide customer support for their SoCs.
Krav
- BS in Electrical Engineering
- Minimum of 10 years of experience in complex technical development
- Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation
- Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques
- Excellent communication skills
- Self-motivated
Önskade kvalifikationer
- Understanding of memory and memory PHY architecture is a plus
Förmåner
- Comprehensive medical and healthcare plans
- ETO and FTO Programs (Time Away)
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP - Purchase Synopsys common stock at a 15% discount
- Retirement Plans
- Competitive salaries
#LPDDR#PHY#IP#design#engineer#semiconductor#ASIC#digital#Verilog#SystemVerilog#linting#synthesis#timing#DFT#power optimization
Företag
Synopsys Inc
Publicerade jobb
för 1 månad sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Bengaluru, India
Kvalifikation
Kandidatexamen
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