The Job

Implementation Engineer, Staff

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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I korthet

Qualcomm India Private Limited seeks a highly talented and technically strong leader to head a team in the Display Sub-System implementation domain. This role requires strong understanding of Physical Synthesis, timing closure, and low-power design methodologies, along with experience in scripting and industry-standard tools like Synopsys and Cadence.

Ansvarsområden

  • Lead a high performing team of engineers in the implementation domain for Display Sub-System.
  • Handle multiple time-critical and complex project executions.
  • Communicate effectively with all stakeholders across the organization.
  • Collaborate with cross-functional teams for best practices and smooth execution.
  • Focus on improving execution efficiency and optimizations in area, power, and performance.
  • Grow the team in technical depth and size.
  • Innovate and bring fresh ideas.
  • Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
  • Development of signoff quality constraints and power intent constraints.
  • May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • TCL script development, running/analyzing/debugging designs.
  • Handle ECOs and formal verification and maintain high quality metrics.

Krav

  • Bachelor’s or master’s degree in engineering with 9-13+ Years of experience.
  • Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
  • Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Experience in all aspects of timing closure for multi-clock domain designs.
  • Familiarity with MCMM synthesis and optimization.
  • Good understanding of low-power design implementation using UPF.
  • Experience with scripting language such as Perl/ Python, TCL.
  • Experience with different power optimization flows or techniques such as clock gating.
  • Ability to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Önskade kvalifikationer

  • Hands on with Synopsys DCG/Genus/Fusion Compiler.
  • Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
  • Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Experience with either RTL development or Physical Design is also a plus.

Förmåner

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
  • Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
#Implementation#Engineer#Staff#Display Sub-System#Hardware Engineering#Physical Synthesis#Synthesis#Timing Constraints#STA#Timing Closure#Low-power Design#UPF#Scripting#Python#Perl#TCL#Power Optimization#Clock Gating#ECOs#Formal Verification#LEC#RTL Lint#CLP#MEMBIST#DFT DRC#Synopsys#Cadence
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Företag

Qualcomm

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

Sökande

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