Ethernet Switch ASIC Design Engineer/Sr
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling
I korthet
Qualcomm China seeks an Ethernet Switch ASIC Design Engineer/Sr in Shanghai. Responsibilities include RTL design, synthesis, timing closure for networking logic, and SoC integration. Requires a Bachelor's degree with 2+ years of ASIC experience and familiarity with Ethernet switching concepts.
Ansvarsområden
- Implement RTL design, synthesis, and timing closure for networking datapath/control logic
- Participate in SoC integration with focus on Ethernet switch subsystems
- Debug functional and performance issues across design, DV, and validation teams
- Collaborate with architecture, firmware, and validation teams to support chip bring-up
Krav
- Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow
- Familiarity with Ethernet switching concepts, such as: L2/L3 forwarding, bridging, routing, packet processing pipelines, basic QoS (queuing, scheduling)
- Fluent in Chinese and English both verbal and written
- Ability to work in stressful situations with tight schedules to meet
Önskade kvalifikationer
- Knowledge of AXI/NoC, PCIe or high-speed interfaces is a plus
- Scripting skills (C/C++, Tcl, Perl) preferred
- Excellent teamwork, interpersonal and communication skills
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
Förmåner
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#ASIC Design#Ethernet Switching#Networking#RTL Design#Verification#Synthesis#Timing Closure#Physical Design#SoC Integration#Chip Bring-up