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Engineer-Staff

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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Qualcomm is seeking a Staff Engineer with 5-10 years of experience in Physical Design, including Synthesis, Place and Route (PnR), and Timing/Power Signoff. The role involves driving PPA optimization, working with advanced technology nodes, and managing timing closure for complex designs. A Bachelor's degree in Engineering or a related field is required, with preferred qualifications including a Master's degree and extensive experience in ASIC design.

Ansvarsområden

  • Drive end-to-end PPA optimization across synthesis-to-PnR boundary.
  • Work on advanced technology nodes, addressing node-specific challenges.
  • Write and tune timing constraints for synthesis, STA, and timing closure.
  • Focus on driving aggressive area recovery, leakage/dynamic power reduction, and Fmax/performance pushes.
  • Perform timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs.
  • Implement low-power designs using UPF, including power gating and multi-voltage domains.
  • Apply power optimization techniques across synthesis and PD.

Krav

  • 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.
  • Strong understanding of Physical Synthesis, Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing.
  • Hands-on experience on advanced technology nodes.
  • Experience with writing and tuning timing constraints.
  • Experience in all aspects of timing closure for MCMM designs.
  • Good understanding of low-power design implementation using UPF.
  • Experience with different power optimization flows/techniques.
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Önskade kvalifikationer

  • Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
  • 6+ years of ASIC design, verification, validation, integration, or related work experience.
  • 2+ years of experience with architecture and design tools.
  • 2+ years of experience with scripting tools and programming languages.
  • 2+ years of experience with design verification methods.
  • 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
  • Proficiency in Python/Tcl and AI Usage.
  • Familiarity with standard software engineering practices like Version Control, Configuration Management, and Regression.
  • Familiar with PnR tools (Innovus/ICC2) and Synthesis tools (Fusion Compiler/Genus).
  • Proven hands-on experience on advanced nodes.
  • Fair knowledge of Static Timing Analysis (PrimeTime/Tempus), LEC, and Low Power (LP) signoff tools.
  • Proficient in VLSI front-end and back-end design steps.
  • Strong PPA mindset.
  • Knowledge of computer architecture and experience in high-speed, low-power processor design will be a plus.

Förmåner

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
  • Details about US benefits available at this link.
#ASIC design#Physical Design#PnR#Timing#Power Signoff#PPA optimization#low-power design#Python#Tcl
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Företag

Qualcomm

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Austin, United States of America

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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