The Job

Display Synthesis, Senior

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Seeking a Senior Display Synthesis Engineer in Bangalore, India, with 3+ years of experience. The role involves synthesis, LEC, low power checks, and constraint validation using industry-standard tools like Synopsys and Cadence. This position offers an opportunity to lead a high-performing team and drive execution efficiency in display sub-system implementation.

Ansvarsområden

  • Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
  • Development of signoff quality constraints and the development of power intent constraints.
  • May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • TCL script development in addition to running/analyzing/debugging designs.
  • Hands on with Synopsys DCG/Genus/Fusion Compiler.
  • Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
  • Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Experience with RTL development or Physical Design is also a plus.
  • Lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.
  • Handle multiple project execution that are time critical and complex.
  • Communicate effectively with all stakeholders across the organization.
  • Collaborate with cross functional teams for upholding the best practices and enabling smooth execution.
  • Focus on improving execution efficiency and improve on the optimizations in area, power and performance.
  • Grow the team in terms of technical depth and size.
  • Innovate and bring fresh ideas.
  • Writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Experience in all aspects of timing closure for multi-clock domain designs.
  • Familiar with MCMM synthesis and optimization.
  • Good understanding of low-power design implementation using UPF.
  • Experience with scripting language such as Perl/ Python, TCL.
  • Experience with different power optimization flows or technique such as clock gating.
  • Work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
  • Handle ECOs and formal verification and maintain high quality matrix.

Krav

  • 3+ years Experience
  • Bachelor’s or master’s degree in engineering with 5+ Years of experience.
  • Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
  • Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Experience in all aspects of timing closure for multi-clock domain designs.
  • Familiar with MCMM synthesis and optimization.
  • Good understanding of low-power design implementation using UPF.
  • Experience with scripting language such as Perl/ Python, TCL.
  • Experience with different power optimization flows or technique such as clock gating.
  • Able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
  • Able to handle ECOs and formal verification and maintain high quality matrix.

Önskade kvalifikationer

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
  • Experience with either RTL development or Physical Design is also a plus.
#Display#Synthesis#Hardware Engineering#Low Power Checks#Memory BIST#Constraints Validation#RTL Lint#CLP#MEMBIST#DFT DRC#TCL Scripting#Synopsys DCG#Genus#Fusion Compiler#Synopsys Prime Time#Cadence Conformal LEC#Cadence Conformal Low Power#UPF#RTL Development#Physical Design#Timing Constraints#STA#Timing Closure#Pipelining#MCMM Synthesis#Low-Power Design#Perl#Python#ECOs#Formal Verification
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Företag

Qualcomm

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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