The Job

Display Synthesis Engineer, Sr Lead

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Qualcomm is looking for a Senior Lead Display Synthesis Engineer in Bangalore, India. This role involves leading a team in the implementation of the Display Sub-System, focusing on physical synthesis, timing closure, and low-power design methodologies using industry-standard tools. The ideal candidate will have 5+ years of experience and strong technical leadership skills.

Ansvarsområden

  • Lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.
  • Handle multiple project execution that are time critical and complex.
  • Communicate effectively with all stakeholders across the organization.
  • Collaborate with cross functional teams for upholding the best practices and enabling smooth execution.
  • Focus on improving execution efficiency and on the optimizations in area, power and performance.
  • Grow the team in terms of technical depth and size.
  • Innovate and bring fresh ideas.
  • Perform Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
  • Develop signoff quality constraints and power intent constraints.
  • Run RTL Lint, CLP, MEMBIST, DFT DRC etc.
  • Develop TCL scripts in addition to running/analyzing/debugging designs.
  • Work with Synopsys DCG/Genus/Fusion Compiler.
  • Work with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
  • Work with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.
  • Write timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Handle all aspects of timing closure for multi-clock domain designs.
  • Perform MCMM synthesis and optimization.
  • Implement low-power design using UPF.
  • Utilize scripting languages such as Perl/ Python, TCL.
  • Apply different power optimization flows or techniques such as clock gating.
  • Work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
  • Handle ECOs and formal verification and maintain high quality matrix.

Krav

  • Bachelor’s or master’s degree in engineering with 5+ Years of experience.
  • Strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
  • Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
  • Experience in all aspects of timing closure for multi-clock domain designs.
  • Familiarity with MCMM synthesis and optimization.
  • Good understanding of low-power design implementation using UPF.
  • Experience with scripting language such as Perl/ Python, TCL.
  • Experience with different power optimization flows or technique such as clock gating.
  • Ability to work independently with design, DFT and PD team for netlist delivery, timing constraints validation.
  • Ability to handle ECOs and formal verification and maintain high quality matrix.
  • 3+ years of experience in Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.
  • Hands on with Synopsys DCG/Genus/Fusion Compiler.
  • Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.
  • Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development.

Önskade kvalifikationer

  • Experience with either RTL development or Physical Design is also a plus.
#Display Synthesis#Hardware Engineering#Synthesis#LEC#Low Power#Memory BIST#Constraints Validation#RTL Lint#CLP#MEMBIST#DFT DRC#TCL Scripting#Synopsys DCG#Synopsys Genus#Fusion Compiler#Synopsys Prime Time#Cadence Conformal LEC#Cadence Conformal Low Power#UPF Development#RTL Development#Physical Design#Display Sub-System#Project Execution#Time Critical#Communication#Cross-functional Collaboration#Best Practices#Execution Efficiency#Optimization#Area#Power#Performance#Technical Depth#Innovation#Physical Synthesis#Timing Constraints#Timing Closure#Pipelining#MCMM Synthesis#Low-power design#Clock Gating#ECOs#Formal Verification#Quality Metrics
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Företag

Qualcomm

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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