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Digital Verification Senior Staff Engineer

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Synopsys is seeking a Digital Verification Senior Staff Engineer in Ho Chi Minh City, Vietnam, to develop and execute verification plans for high-speed mixed-signal PHY IPs. This role involves RTL and gate-level simulations, debugging complex failures, and collaborating with cross-functional teams to ensure the reliability and efficiency of semiconductor products.

Ansvarsområden

  • Develop and execute verification plans for high-speed mixed-signal PHY IPs, defining coverage goals, test scenarios, and success criteria.
  • Perform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments.
  • Build functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks.
  • Generate VCD files and run power analysis using PrimeTime PX, correlating simulation activity with power consumption.
  • Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes.
  • Collaborate with design, analog, and integration teams to align verification strategy with IP architecture.
  • Review and refine verification infrastructure, identifying coverage gaps and proposing new tests to close them.

Krav

  • 5+ years of hands-on experience in ASIC RTL design flow with strong focus on verification and debugging.
  • Demonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLS.
  • Proficiency in SystemVerilog and experience working within UVM-based verification environments.
  • Strong debugging skills across waveform analysis, coverage review, and simulation log interpretation.
  • Experience with power analysis tools such as PrimeTime PX, including VCD generation.
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.

Önskade kvalifikationer

  • Knowledge of high-speed interface protocols like DDR PHY, HBM PHY, or UCIe PHY is a strong plus.
  • Ability to look at a failing gate-level simulation and zero in on the signals that matter, then explain what broke and why without needing slides.
  • Treat verification plans as hypotheses to be tested, not checklists, and revise them when you discover gaps.
  • Communicate clearly with design engineers and architects, translating between abstraction levels without losing technical precision.
  • Stay calm when a regression fails before a milestone and methodically work the problem instead of guessing at fixes.
  • Comfortable working in English across global teams, writing clear bug reports and participating in technical discussions.

Förmåner

  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs for time away
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP with a 15% discount and 24-month look-back
  • Retirement plans (vary by region and country)
  • Competitive salaries
#Digital Verification#Senior Staff Engineer#RTL#GLS#High-Speed Interface#PHY IP
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Företag

Synopsys Inc

Publicerade jobb

för 2 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Ho Chi Minh City, Vietnam

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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