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Design Verification Engineer

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Microsoft is seeking a Design Verification Engineer to join their Artificial Intelligence Silicon Engineering (AISiE) team. This role involves leading the verification of complex silicon designs at the SOC, subsystem, or IP levels, developing verification environments, and debugging RTL designs using various methodologies.

Ansvarsområden

  • Own or lead verification of complex flows at the SOC, subsystem, or IP levels.
  • Plan the verification of complex design IP/SoC interacting with architecture and design engineers to identify verification test scenarios.
  • Learn about the design and interact with partner teams to define verification strategies and test plans.
  • Develop verification environments and run and debug simulations to drive quality.
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
  • Innovate to improve verification efficiency through methodologies or tools.
  • Coach and mentor others in your areas of expertise.
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Krav

  • 8-16 years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s.
  • Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++.
  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
  • Scripting language such as Python or Perl.
#Silicon Engineering#Hardware Engineering
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Företag

Microsoft

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

Hybrid

Erfarenhetsnivå

Senior

Platser

United States

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