DDR STA/Timing Engineer (Staff/ Senior Staff)
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I korthet
Qualcomm is looking for a highly experienced DDR STA/Timing Engineer (Staff/ Senior Staff) to join their Hardware Engineering team in Bangalore, India. This role involves planning, designing, optimizing, verifying, and testing electronic systems with a focus on Static Timing Analysis (STA) and timing convergence across various design complexities and technology nodes.
Ansvarsområden
- STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
- Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Work on automation scripts within STA/PD tools for methodology development.
- Technical writing and communication, working in a cross-collaborative environment.
- Design automation using TCL/Perl/Python.
- Familiarity with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus.
- Familiarity with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.
Krav
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
- 7 to 13 years of experience in STA/Timing.
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Prime-time, Tempus.
- Experience in driving timing convergence at Chip-level and Hard-Macro level.
- In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
- Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
- Proficient is scripting languages – TCL, Perl, Awk.
- Basic knowledge of device physics.
Önskade kvalifikationer
- B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.
Förmåner
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#Hardware Engineering#STA#Timing Analysis#DDR#VLSI
Företag
Qualcomm
Publicerade jobb
för 3 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Bangalore, India
Kvalifikation
Kandidatexamen, Masterexamen, Doktorand
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