DDR Design Verification Lead Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Qualcomm seeks a lead Design Verification engineer for LPDDR/DDR IPs and Subsystems. Responsibilities include creating DV infrastructure, test plans, debugging, and ensuring high-quality verification. Requires a Bachelor's degree in Engineering and 11+ years of hardware engineering experience.

Ansvarsområden

Create DV infrastructure for verification
Integrate VIP's
Create and execute test plans
Debug failures
Write assertions
Close code and functional coverage
Ensure high quality verification
Working with all stakeholders to ensure program success

Krav

Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.
11+ years Hardware Engineering experience or related work experience.
Strong Debug, UVM, System Verilog
Understanding Specs and Standards and developing relevant test plans
Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
4+ Year of industry experiences in the following areas:
Thorough understanding of Digital design concepts
Thorough understanding dv methodologies and tools
Good understanding of DDR/LPDDR families (LP/PC) and generations (DDR2/3/4/5)
Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite

Förmåner

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.