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Custom CPU Physical Design Engineer (Lead/Staff/Sr Staff)

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Qualcomm India Private Limited is looking for a Custom CPU Physical Design Engineer at the Lead, Staff, or Senior Staff level in Bangalore, India. This role involves planning, designing, and optimizing electronic systems, with a focus on physical design and timing signoff for high-speed cores, adhering to PPA targets and PDN methodology. A strong background in IC design and physical design activities, including RTL to GDSII implementation, is required.

Ansvarsområden

  • Plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
  • Collaborate with cross-functional teams to develop solutions and meet performance requirements.
  • Lead physical design, STA and PDN activities for block level or chip level.
  • Work independently in the areas of RTL to GDSII implementation.
  • Collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
  • Handle technical deliveries with a small team of engineers.

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
  • 5 to 16 yrs experience in Physical Design and timing signoff for high speed cores.
  • Good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.
  • Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC design.
  • Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
  • Circuit level comprehension of time critical paths in the design.
  • Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
  • Tcl/Perl scripting
  • Strong problem-solving skills.

Önskade kvalifikationer

  • Experience in leading block level or chip level Physical Design, STA and PDN activities.
  • Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
  • Willing to handle technical deliveries with a small team of engineers.

Förmåner

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process.
  • Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
  • Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
#Physical Design#timing signoff#high speed cores#PPA targets#PDN methodology#IC design#STA#PDN activities#RTL to GDSII implementation#constraints validation#verification#low power flow#power gating#multi-Vt flow#power supply management#time critical paths#deep sub-micron design#leakage power#signal integrity#DFM#Tcl/Perl scripting
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Företag

Qualcomm

Publicerade jobb

för 4 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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