CPU Physical Design Timing Engineer
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Qualcomm is seeking a CPU Physical Design Timing Engineer to join Nuvia (now part of Qualcomm) in Santa Clara, California. The role involves defining, developing, and driving CPU timing closure for Oryon CPU Cores, including developing timing constraints, meeting PPA goals, and coding automation scripts. Collaboration with microarchitecture, RTL design, and central timing teams is expected.
Ansvarsområden
- Define, develop and drive CPU timing closure for Oryon CPU Cores.
- Work with microarchitecture and RTL design teams to develop timing constraints.
- Drive implementation to meet aggressive power, area, and performance goals using industry standard tools/flows.
- Code automation scripts for STA native tools and CPU timing infrastructure and methodology.
- Collaborate with Qualcomm central timing technology & methodology team.
- Interact with CPU implementation team to drive PPA goals of CPU.
- STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
- Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Find root cause of timing miscorrelation and propose solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Technical writing and communication skills.
- Work in a cross-collaborative environment.
Krav
- Excellent automation skills using TCL/Perl/Python.
- Ability to develop/work on automation scripts with the given spec to develop CPU STA signoff flow / methodology.
- Familiar with digital flow design implementation RTL to GDS : ICC, Innovus , PT/Tempus.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant work experience.
- OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant work experience.
- OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant work experience.
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Prime-time, Tempus.
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
Önskade kvalifikationer
- History of any framework /tool /utility development is preferred.
- Have experience in driving timing convergence at Chip-level and Hard-Macro level.
- In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
- Basic knowledge of device physics.
Förmåner
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Opportunity to work on industry leading technology nodes N2/N3.
- Opportunity to carve out a strong professional growth path.
#CPU#Physical Design#Timing Closure#STA#ASIC#Nuvia#Qualcomm
Företag
Qualcomm
Publicerade jobb
för 1 dag sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Mellannivå
Platser
Santa Clara, United States of America
Kvalifikation
Kandidatexamen, Masterexamen, Doktorand
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