ASIC/SoC Design Verification Senior / Staff Engineer
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning
I korthet
Synopsys is seeking a Senior/Staff ASIC/SoC Design Verification Engineer in Ho Chi Minh City, Vietnam, to design and develop cutting-edge semiconductor solutions. The role involves full RTL functional verification lifecycle, UVM-based environment development, and debugging complex issues. The ideal candidate has 3+ years of experience in ASIC/SoC verification and strong skills in Verilog, System Verilog, UVM, and scripting.
Ansvarsområden
- Execute the full RTL functional verification lifecycle for IP, subsystem, and SoC projects, from verification planning through coverage closure and signoff
- Develop and maintain UVM-based verification environments, building reusable components and test infrastructures that scale across projects
- Drive verification planning, define functional coverage models, write System Verilog Assertions, and execute strategies that ensure high-quality design deliverables
- Debug complex design and verification issues using VCS and Verdi, performing root-cause analysis and coordinating with cross-functional teams
- Collaborate with global Synopsys teams to deliver projects on schedule while meeting customer quality expectations
- Interface directly with customer engineering teams to define project scope, establish verification strategies, and drive key deliverables (L3 and L4 roles)
- Mentor junior verification engineers and contribute to continuous improvement of verification methodologies and best practices (L3 and L4 roles)
Krav
- 3+ years of hands-on experience in ASIC/SoC Design Verification, with strong understanding of end-to-end verification flows from planning through signoff
- Proficiency in Verilog and System Verilog, with strong debugging and root-cause analysis skills using tools like VCS and Verdi
- Solid expertise in UVM-based verification environments and experience developing reusable verification components
- Experience developing System Verilog Assertions, functional coverage models, and coverage-driven verification methodologies
- Strong scripting and automation skills using Python, Perl, or Shell scripting
- Thorough understanding of AMBA protocols (AXI, AHB, APB) and experience verifying complex bus-based systems
Önskade kvalifikationer
- Knowledge of high-speed interface protocols such as USB, PCIe, UCIe, DDR, or Ethernet is a strong plus
- Ability to take a 500-page protocol spec, identify verification-critical sections, and build a coverage plan that actually maps to what could go wrong in silicon
- Methodical debugging approach, forming hypotheses and instrumenting the right signals
- Clear communication of technical tradeoffs
- Care about engineers who will inherit your testbench, writing code and documentation that makes their job easier
- Stay current with verification methodologies and tools
Förmåner
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
#ASIC#SoC#Design Verification#Engineering#Senior Engineer#Staff Engineer
Företag
Synopsys Inc
Publicerade jobb
för 1 dag sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Ho Chi Minh City, Vietnam
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