ASICS Design Verification Engineer-Senior

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning

I korthet

Qualcomm is looking for a Senior ASICS Design Verification Engineer in San Diego, CA. The role involves comprehensive pre-silicon test planning, testbench development using SystemVerilog-UVM, and formal verification for digital power IP. The engineer will also work on automation to enhance verification efficiency.

Ansvarsområden

Responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
Involves comprehensive pre-silicon test planning for digital power IP's.
Develop testbench using advanced verification methodology such as SystemVerilog-UVM.
Develop coverage and assertion models.
Perform formal verification (property checking).
Learn and deploy power-aware UPF verification flow and methodology.
Involve in developing automation to improve verification efficiency.

Krav

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
2+ years of experience with ASIC design and verification tools, techniques, and methodology.
Experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
Experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
Experience with developing block-level testbench environment using SystemVerilog.
Experience with verification methodologies through coursework or past experiences such as UVM or OVM.
Experience with scripting/automation skills using either Perl or python.

Önskade kvalifikationer

Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
6+ years of experience with ASIC design and verification tools, techniques, and methodology.
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
6+ years of experience with developing block-level testbench environment using SystemVerilog.
6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
6+ years of experience with scripting/automation skills using either Perl or python.
Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).

Förmåner

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.

Färdigheter

SystemVerilogUVMVerilogVHDLC++CPerlPythonAXIAHBAPB

#ASIC#Design Verification#Engineering#Digital Power IP#Test Planning#Testbench Development#SystemVerilog-UVM#Coverage Development#Assertion Model Development#Formal Verification#Property Checking#Power-Aware UPF#Automation#Verification Efficiency#RTL#Computer Architecture#Object-Oriented Programming#AMBA Bus Protocol