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ASICS Design Verification Engineer

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I korthet

Qualcomm is looking for an ASICS Design Verification Engineer in Vancouver, British Columbia. This role involves comprehensive pre-silicon test planning, testbench development using SystemVerilog-UVM, and formal verification. A Bachelor's degree in Engineering or Science with 2+ years of experience is required.

Ansvarsområden

  • Responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
  • Comprehensive pre-silicon test planning for digital power IP's.
  • Testbench development using advanced verification methodologies such as SystemVerilog-UVM.
  • Coverage development and assertion model development.
  • Formal verification (property checking).
  • Learn and deploy power-aware UPF verification flow and methodology.
  • Develop automation to improve verification efficiency.

Krav

  • Bachelor's degree in Engineering, Science, or a closely related field.
  • 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • OR PhD in Science, Engineering, or related field.

Önskade kvalifikationer

  • Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
  • 6+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
  • 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
  • 6+ years of experience with developing block-level testbench environment using SystemVerilog.
  • 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
  • 6+ years of experience with scripting/automation skills using either Perl or python.
  • Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
  • Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).

Förmåner

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
#ASIC#Verification#Design#Engineer
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Företag

Qualcomm

Publicerade jobb

för 2 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Mellannivå

Platser

Vancouver, Canada

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

Sökande

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