ASIC Logic Design Verification Principal Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Synopsys is looking for a Principal Engineer in ASIC Logic Design Verification with over a decade of experience. This role involves architecting UVM environments, writing System Verilog test sequences, and mentoring junior engineers to ensure the delivery of high-quality, verified interface IP designs.

Ansvarsområden

Collaborate with design teams to define verification requirements and translate specs into test plans.
Architect and implement UVM testbench environments.
Write System Verilog test sequences and constrained random stimulus.
Implement System Verilog Assertions for functional and formal verification flows.
Build and analyze functional and code coverage metrics.
Lead and mentor a team of verification engineers.

Krav

Bachelor's or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering.
12+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification.
Deep expertise in System Verilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification.
Proven experience implementing System Verilog Assertions for functional and formal verification flows.
Strong programming skills in at least two of: C, System Verilog, TCL, Perl, or Python.

Önskade kvalifikationer

Experience with PCI Express and CXL protocols is a strong plus.
Experience in interface IP verification, formal verification tools like Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will set you apart.
Ability to spot verification gaps and articulate their importance.
Precision and respect in code reviews.
Proactive approach to work with available information.
Natural ability to teach and explain complex concepts.

Förmåner

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
Purchase Synopsys common stock at a 15% discount.
Retirement plans.
Competitive salaries.

#ASIC#Logic Design#Verification#Principal Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#UVM#System Verilog#PCI Express#CXL

Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Ledning

Platser

Dublin, Ireland

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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