The Job

ASIC Digital Design , Staff Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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Synopsys is hiring a Staff Engineer for ASIC Digital Design in Bengaluru. This role involves architecting and implementing RTL designs for high-speed IP cores, driving synthesis and timing analysis, and mentoring junior engineers. The position requires a Bachelor's or Master's degree in a relevant field and 4+ years of experience in ASIC RTL design.

Ansvarsområden

  • Architect and implement RTL designs for DesignWare IP cores targeting commercial, enterprise, and automotive applications, translating protocol specifications into detailed micro-architectures and design documentation
  • Own hands-on RTL coding in synthesizable Verilog/SystemVerilog for medium to high complexity features, including data path logic like Reed Solomon FEC, BCH codes, CRC engines, and MAC SEC implementations
  • Drive synthesis, static timing analysis, CDC analysis, lint checking, and P&R-aware synthesis using tools like Fusion Compiler, ensuring designs meet area, latency, and throughput targets at 600MHz+
  • Collaborate with global engineering teams and engage directly with customers to refine specifications, resolve design ambiguities, and align on feature requirements
  • Lead technical reviews, debug complex RTL issues across simulation and synthesis, and develop test strategies that ensure design quality and coverage
  • Mentor and technically lead a team of RTL designers, providing guidance on coding practices, design trade-offs, timing closure techniques, and process improvements
  • Manage design flows using version control systems like Perforce and automate repetitive tasks with Perl or Shell scripting to improve team efficiency

Krav

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related technical field
  • 4+ years of hands-on industry experience in ASIC RTL design, with a track record of delivering completed IP cores or complex digital subsystems to production
  • Deep expertise in data path and control path design, including practical experience with Reed Solomon FEC, BCH codes, CRC architectures, MAC SEC engines, or similar error correction and security logic
  • Strong proficiency in synthesizable Verilog/SystemVerilog coding, simulation, and design flows including lint, CDC analysis, synthesis, and static timing analysis
  • Experience with high-speed design targeting 600MHz+ clock frequencies, P&R-aware synthesis techniques, and timing closure in advanced process nodes
  • Familiarity with industry-standard protocols such as Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, or AMBA (AHB, AXI), and the ability to read and implement from protocol specifications
  • Experience with version control systems like Perforce and scripting languages such as Perl or Shell for design automation and flow management

Önskade kvalifikationer

  • Prior experience as a technical lead or mentor is a strong plus
  • You can sit in a spec review with a customer, hear a vague requirement about latency tolerance, and walk out with a clear architecture sketch that addresses the real constraint without overbuilding
  • You are the engineer who catches the CDC violation in code review before it gets to simulation, and you explain why it matters in a way that helps the junior designer learn, not just fix
  • You are comfortable leading a technical discussion with a distributed team across Bangalore, Sunnyvale, and Taipei, keeping everyone aligned on the critical path without losing the details that matter
  • You debug with discipline, you do not guess, you form hypotheses, you instrument the design, you trace signals, and you document what you find so the next person does not hit the same issue
  • You have a point of view on design trade-offs, area versus latency, pipeline depth versus clock frequency, and you can articulate those trade-offs to an architect or a verification lead in two sentences without losing the nuance
  • You stay current with industry trends, new protocols, emerging standards, and EDA tool capabilities, and you bring that knowledge back to your team to improve how you all work

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#asic#digital design#staff engineer#hardware engineer#semiconductor#rtl design#verilog#systemverilog#pci#ethernet#ddr#usb#eda#designware ip cores
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Företag

Synopsys Inc

Publicerade jobb

för 1 dag sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen

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