The Job

ASIC Digital Design , Staff Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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I korthet

Synopsys is seeking a Staff Engineer, ASIC Digital Design, in Bengaluru, India. This role involves designing and coding RTL for high-speed Ethernet IP cores, translating specifications into micro-architectures, and collaborating with global teams. The ideal candidate has a Bachelor's in Electrical Engineering with 6+ years of ASIC/IP design experience and strong Verilog/SystemVerilog skills.

Ansvarsområden

  • Design and code RTL for high-speed Ethernet IP cores (100G to 1.6T), focusing on low latency and timing closure.
  • Translate protocol specifications into micro-architecture and detailed design documents for various IP domains (Ethernet, AMBA, PCIe, USB, MIPI, memory controller).
  • Build and refine Verilog testbenches to improve functional and code coverage.
  • Perform technical reviews of functional specs, micro-architecture documents, and RTL code from peers.
  • Drive timing analysis and closure using synthesis, STA, lint, CDC, and formal verification flows.
  • Apply low power design methodologies and automotive safety requirements.
  • Collaborate with verification, integration, and product teams across global sites.

Krav

  • Bachelor's in Electrical Engineering with 6+ years of hands-on ASIC or IP design experience, or Master's with 4+ years.
  • Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers.
  • Strong working knowledge of at least one protocol: AMBA (AHB, AXI, CHI), SD, eMMC, DDR, PCIe, USB, MIPI.
  • Proven ability to create micro-architecture and detailed design documents from functional specs.
  • Hands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools.
  • Solid understanding of high-speed, low-latency design techniques and timing closure challenges.
  • Familiarity with Perforce or similar version control systems, and scripting in Perl or shell for automation.

Önskade kvalifikationer

  • High-speed Ethernet (100G and above) experience is a strong plus.
  • Experience with datapath designs or arithmetic algorithms like FEC is a plus.
  • Ability to take a vague feature request and turn it into a clean, implementable design.
  • Ability to catch subtle issues during RTL review and explain them clearly.
  • Ability to prioritize tasks effectively.
  • Clear written and verbal communication skills for cross-timezone collaboration.
  • Ability to push back constructively on ambiguous specs or unrealistic schedules.
  • Treats documentation as part of the design.

Förmåner

  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs for time away.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP to purchase Synopsys common stock at a 15% discount.
  • Retirement plans (vary by region and country).
  • Competitive salaries.
#ASIC#Digital Design#Staff Engineer#RTL#IP Cores#Ethernet#AMBA#AXI#CHI#PCIe#USB#MIPI#Memory Controller#Timing Closure#Low Power Design#Automotive Safety#Verification#Synthesis#STA#Lint#CDC#Formal Verification#Verilog#SystemVerilog#Perforce#Perl#Shell Scripting
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Företag

Synopsys Inc

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen

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