The Job

ASIC Digital Design, Sr Staff Engineer - DDR/LPDDR

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning

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I korthet

Synopsys is looking for a Senior Staff Engineer in ASIC Digital Design with expertise in DDR/LPDDR protocols. This role involves leading verification teams, developing SystemVerilog/UVM environments, and ensuring the quality and signoff of IP cores. The position is based in Hyderabad, India, and requires a Bachelor's or Master's degree in Electrical Engineering or equivalent with 6+ years of experience.

Ansvarsområden

  • Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff
  • Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations
  • Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team
  • Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable
  • Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time
  • Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and catch issues early
  • Manage regression infrastructure and work with the infra team to keep verification cycles efficient and reliable

Krav

  • Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 6+ years of hands-on verification experience
  • Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff
  • Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow
  • Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs
  • Proficiency extracting and interpreting functional coverage and code coverage, and using those metrics to drive verification closure
  • Experience verifying serial interface protocols and working through IP design and verification processes
  • Knowledge of DDR or LPDDR protocols is a strong plus
  • Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff
  • Experience with AI-assisted verification tools is a plus

Önskade kvalifikationer

  • You can explain a coverage hole to an architect in two sentences and walk out with a plan to close it
  • You debug by hypothesis, not by adding print statements until something makes sense
  • When a testbench is too slow or too brittle, you refactor it instead of working around it
  • You give feedback that makes engineers better, not just feedback that makes the code pass
  • You work across time zones and teams without losing context or creating confusion downstream
  • You know when to push back on a design decision and when to adjust the verification plan to match reality
  • AI-assisted verification flows

Förmåner

  • Competitive salaries
  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement Plans
#ASIC#Digital Design#DDR#LPDDR#Sr Staff Engineer#Engineering#Synopsys#Hardware Engineers#semiconductor solutions#chip architecture#circuit design#verification#SystemVerilog#UVM#DesignWare IP
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Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hyderabad, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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