The Job

ASIC Digital Design, Sr Staff Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

Gå med för uppdateringar

I korthet

Synopsys is looking for a Senior Staff Engineer to design complex ASIC digital subsystems. The role involves owning the full lifecycle from architecture to release, including RTL development, verification collaboration, and low power design. The ideal candidate has 8+ years of RTL design experience with multiple tape-outs.

Ansvarsområden

  • Own the full lifecycle of complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and final release
  • Craft subsystem architecture and functional specifications, define micro-architecture, and write production-quality RTL using industry best practices
  • Drive RTL quality checks including lint, CDC, RDC, and work closely with verification teams to ensure functional correctness and coverage closure
  • Integrate and design around standard protocols including PCIe, DDR, UFS, USB, and AMBA-based interconnects
  • Implement low power design techniques across clock gating, power gating, and multi-voltage domains, ensuring power intent is captured and verified
  • Collaborate with logic synthesis, STA, and physical design teams to ensure timing closure, develop synthesis constraints, and resolve equivalence check issues
  • Work with DFT teams to architect scan, MBIST, and other testability features into your subsystems from the start

Krav

  • Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or equivalent technical field
  • 8+ years of hands-on RTL design experience with multiple tape-outs under your belt, ideally in complex IP, subsystems, or SoC blocks
  • Deep proficiency with Verilog or SystemVerilog and proven ability to write synthesizable, timing-clean, low power RTL at scale
  • Strong working knowledge of standard protocols such as PCIe, DDR, UFS, USB, or AMBA (AXI, AHB, APB)
  • Hands-on experience with low power design techniques including clock gating, power gating, retention, UPF, and multi-voltage domain architecture
  • Solid understanding of logic synthesis, constraint development (SDC), static timing analysis (STA), and equivalence checking flows
  • Familiarity with DFT concepts including scan insertion, ATPG, MBIST, and how testability requirements shape design architecture, experience working directly with DFT teams is a plus

Önskade kvalifikationer

  • You can take a high-level requirement document and turn it into a clean subsystem architecture without needing every detail spelled out for you
  • You write RTL that passes lint, CDC, and synthesis checks on the first pass because you think about those constraints while you code, not after
  • You can sit in a room with verification engineers, implementation leads, and DFT architects and walk out with a plan that actually works for everyone
  • You push back when a specification is ambiguous or a timeline does not account for real design complexity, and you do it in a way that moves the conversation forward
  • You are organized enough to manage multiple release phases, cross-functional dependencies, and shifting priorities without dropping threads
  • You care about the quality of what you release, not just hitting the schedule, and you know how to balance both

Förmåner

  • Competitive salaries
  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP (Purchase Synopsys common stock at a 15% discount, with a 24 month look-back)
  • Retirement Plans
#ASIC#Digital Design#RTL#Verilog#SystemVerilog#PCIe#DDR#UFS#USB#AMBA#Low Power Design#STA#DFT
Synopsys Inc Logo

Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

Ansök tidigt