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ASIC Digital Design, Principal Engineer

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Synopsys is hiring a Principal Engineer for ASIC Digital Design in Moreira, Portugal. This role involves designing and developing cutting-edge semiconductor solutions, focusing on high-speed communication protocols like DDR and HBM, and mentoring junior engineers. The ideal candidate has over 10 years of experience in digital logic design that holds up in silicon.

Ansvarsområden

  • Define micro-architecture for mixed-signal IP blocks from industry specifications and internal architecture definitions, balancing performance, power, area, latency and timing for HPC applications
  • Develop RTL for complex digital blocks within high-speed communication IP, including DDR and HBM interfaces
  • Model circuit behavior for analog and mixed-signal components to enable co-design and early validation
  • Define and refine synthesis constraints, working closely with physical design and timing closure teams to ensure your blocks meet targets
  • Run and review code quality checks (Lint, CDC and RDC analysis), catching issues early in the development cycle
  • Evaluate design trade-offs across multiple dimensions and recommend solutions that align with product goals and market requirements
  • Mentor engineers on your team, reviewing designs, providing technical guidance, and helping them build the judgment that comes with experience

Krav

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field
  • 10+ years of hands-on ASIC digital design experience, with a strong track record of blocks that have taped out and worked
  • Deep expertise in high-speed communication protocols, specifically DDR, HBM, or similar memory interfaces
  • Solid understanding of low power design techniques and how to apply them in performance-critical contexts
  • Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) analysis, and experience resolving violations in complex designs
  • Experience with synthesis flows, including physical-aware synthesis and constraint definition for timing closure
  • Familiarity with mixed-signal design environments and the ability to work effectively with circuit designers and behavioral models is a strong plus

Önskade kvalifikationer

  • You can walk into a room with architects, analog designers, and verification engineers, listen to three conflicting constraints, and walk out with a design approach that actually works for all of them
  • When you review RTL, you do not just check for syntax. You are looking at the structure, the reusability, the assumptions baked into the logic, and whether it will hold up under corner cases
  • You are process-oriented in the best sense. When something breaks, you want to know why it broke and what upstream decision allowed it to happen, not just how to patch it
  • Detail matters to you. You catch the subtle bugs, the edge cases in the spec, the constraint that is slightly off, because you know those are the things that cost weeks in the lab later
  • You are comfortable navigating a multi-team environment where your block touches verification, physical design, circuit design, and system architecture, and you know how to keep all those threads aligned without losing momentum
  • You take mentorship seriously. You make time to review a junior engineer's design, explain why a different approach might scale better, and help them build the instincts that only come from doing the work

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#ASIC#Digital Design#Principal Engineer
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Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Ledning

Platser

Moreira, Portugal

Kvalifikation

Masterexamen

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