ASIC Digital Design Manager

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Synopsys is looking for an experienced ASIC Digital Design Manager in Bengaluru, Karnataka, India to lead a team in developing Ethernet MAC and PCS IP. The role requires a strong background in RTL development, microarchitecture, and technical leadership, with a focus on delivering high-quality semiconductor solutions.

Ansvarsområden

Lead a team of digital design engineers developing Ethernet MAC and PCS IP from microarchitecture specification through customer release
Drive architectural and microarchitectural decisions for next-generation Ethernet controllers, translating customer requirements into robust, scalable RTL implementations in SystemVerilog
Oversee design reviews, timing closure strategy, CDC/RDC sign-off, and synthesis quality across multiple concurrent IP development projects
Manage resource allocation, project execution, and cross-functional collaboration with verification, physical design, and product teams to meet schedule and quality commitments
Conduct technical interviews, assess candidate capabilities in RTL design and microarchitecture, and build a high-performing team through hiring and onboarding
Mentor engineers on complex implementation challenges including high-speed interface design, multi-voltage domain architectures, and UPF-based low-power methodologies
Own performance reviews, career development planning, and succession planning for your team while fostering a culture of technical excellence and continuous learning

Krav

10+ years of hands-on ASIC digital design experience with deep expertise in RTL development, microarchitecture, and IP design
3+ years in a technical leadership or engineering management role, with demonstrated ability to lead, mentor, and grow design teams
Expert-level proficiency in SystemVerilog and Verilog for synthesis, with a strong track record of delivering production-quality RTL
Deep knowledge of high-speed interfaces and protocols such as Ethernet, PCIe, DDR, or AMBA AXI/AHB/APB
Strong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals
Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies

Önskade kvalifikationer

Experience with low-power design techniques, UPF-based power intent definition, and multi-voltage domain architectures is a strong plus
Familiarity with advanced process nodes (7nm, 5nm, or below) or hardware/software co-verification using emulation platforms like Palladium or Zebu is a plus

Förmåner

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP - Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans
Competitive salaries

Färdigheter

SystemVerilogVerilogEthernetPCIeDDRAMBA AXIAHBAPBStatic Timing AnalysisCDCRDCUPF

#ASIC#Digital Design#Manager#Engineering#RTL#Microarchitecture#IP Design#SystemVerilog#Ethernet#Semiconductor

Om Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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