ASIC Digital Design, Architect
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system
I korthet
Synopsys seeks an experienced ASIC Digital Design Architect to design high-speed SerDes IP (Ethernet, PCIe, SATA, USB) for cutting-edge semiconductor solutions. This role requires 10+ years of digital ASIC design experience, strong RTL design skills in Verilog/VHDL, and expertise in clock domain crossing, synthesis, and DFT. The position offers hybrid or remote work across Canada and involves mentoring junior engineers.
Ansvarsområden
- Architect and design digital subsystems for high-speed SerDes IP including Backplane Ethernet, PCIe, SATA, and USB 2/3 PHYs
- Analyze and define digital and analog interface specifications, translating system-level requirements into implementable RTL and design constraints
- Drive design flow decisions for clock domain crossing, synthesis, DFT insertion, and low-power architecture across complex mixed-signal blocks
- Collaborate directly with ASIC verification engineers to define testplans, review assertion and code coverage, and close functional coverage gaps
- Perform gate-level simulation, analyze timing and power, and debug failure cases across digital and mixed-signal boundaries
- Mentor junior design engineers on RTL quality, design intent, synthesis impact, and cross-functional collaboration
- Work across design groups and customer support teams to resolve design issues, clarify specifications, and support silicon bring-up
Krav
- Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience
- 10+ years of hands-on digital ASIC design experience, with significant work in high-speed or mixed-signal environments
- Strong proficiency in Verilog or VHDL for RTL design and gate-level simulation
- Deep understanding of clock domain crossing design, analysis, and verification methodologies
- Hands-on experience with synthesis tools and techniques, including timing closure and power optimization
- Solid knowledge of DFT methodologies including scan insertion, ATPG, and boundary scan
- Experience working closely with verification teams on testplan creation, coverage closure, and failure analysis
Önskade kvalifikationer
- Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB is a strong plus.
Förmåner
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount
- Retirement plans
- Competitive salaries
#ASIC#Digital Design#Architecture#Hardware Engineering#Semiconductor#Chip Architecture#Circuit Design#Verification#SerDes#Clock Domain Crossing#RTL#Verilog#Synthesis#DFT#Mixed-Signal#Timing#Noise#Power#Ethernet#PCIe#SATA#USB