The Job

ASIC Design / Verification, Manager-Sr Manager

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I korthet

Synopsys is looking for an experienced ASIC Design/Verification Manager-Sr Manager in Hsinchu, Taiwan. This role involves leading teams in the design and verification of IP cores and SOCs, utilizing Verilog/System Verilog and UVM, and contributing to cutting-edge semiconductor solutions. The ideal candidate has extensive experience in memory protocols and a proven track record of team leadership.

Ansvarsområden

  • Specify, design/architect, and implement IP Design and/or Verification environments for synthesizable DesignWare cores.
  • Lead a team, guiding them towards the closure of day-to-day design and/or verification activities.
  • Work closely with RTL designers, Architects, and Verification Engineers as part of a global team.
  • Understand design specifications and develop RTL code, test plans, and testbenches at both unit and system levels.
  • Ensure product release milestones are met through effective regression debug triaging and verification activities.
  • Contribute to the development and implementation of NextGen DesignWare HBM IPs, fostering a culture of continuous improvement and innovation.

Krav

  • BS/MS in EE/EC/VLSI with 15+ years of relevant experience in the verification of IP cores and/or SOC.
  • Experience in leading a team of engineers and guiding them towards achieving project milestones.
  • Hands-on experience in RTL design and/or verification of complex designs at the IP or SoC level.
  • Strong knowledge of Verilog/System Verilog and experience in developing testbenches in UVM environments.
  • Experience with memory protocols like HBM/DDR/LPDDR and familiarity with IP design and verification tools.
  • Proficiency in Perl/Python-based automation and excellent communication and problem-solving skills.

Önskade kvalifikationer

  • A strong team leader and motivator with a go-getter attitude.
  • A technical contributor with expertise in System Verilog/Verilog RTL coding and testbench development.
  • Capable of creating deliverables that meet high standards without requiring close supervision.
  • Skilled in understanding design and verification milestones and aligning team tasks accordingly.
  • Experienced in improving coverage metrics and defining additional test cases.
  • Familiar with HDLs such as Verilog and scripting languages like shell/Perl/Python.
  • A good team player with strong interpersonal and communication skills.
  • Highly motivated and self-propelled, thriving in a project and team-oriented environment.

Förmåner

  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Retirement Plans
  • Competitive salaries
#ASIC#Design#Verification#Manager#Sr Manager#Hardware Engineers#Semiconductor Solutions#Chip Architecture#Circuit Design#IP Cores#SOC#Verilog#System Verilog#UVM#HBM#DDR#LPDDR#Perl#Python
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Företag

Synopsys Inc

Publicerade jobb

för 2 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hsinchu, Taiwan

Kvalifikation

Kandidatexamen, Masterexamen

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