ASIC Design Verification Engineer, Principal
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Synopsys is seeking a Principal ASIC Design Verification Engineer in Hsinchu, Taiwan, to lead verification strategies and testbench development for cutting-edge semiconductor solutions. This role requires extensive experience in SystemVerilog, UVM, and SoC/ASIC design flows, with a focus on advancing technology in areas like AI and IoT.
Ansvarsområden
- Develop verification strategies and plans for ASIC/SoC projects
- Define and implement testbench architecture and methodologies
- Build testbench infrastructure and verification components
- Create verification item lists, coverage models, and checkers
- Provide clear, metric-driven reports on verification progress
- Break down tasks, develop schedules, and manage deliverables
- Lead and coordinate design review meetings
- Serve as a technical expert and mentor within the team
Krav
- Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 15+ years of relevant experience
- Extensive hands-on experience creating test environments from functional specifications using UVM/VMM/OVM
- Proven expertise in constraint random verification, coverage closure, and failure analysis
- Proficiency in SystemVerilog, UVM, and object-oriented verification methodologies
- Experience with Verilog/SystemVerilog coding and simulation tools
- Solid understanding of SoC/ASIC design flows and backend processes
- Knowledge of one or more interface protocols: DDR, PCIe, AMBA (AMBA2, AXI, CHI), SD, eMMC, Ethernet, USB, MIPI
- Experience working in Unix environments
- Strong English communication skills, both written and verbal
- Ability to work independently, drive innovation, and solve complex problems
- Strong team player with excellent interpersonal skills
Önskade kvalifikationer
- Experience with formal verification techniques
- Knowledge of C/C++, Perl, Python, and TCL scripting
- Understanding of firmware or embedded software development
- Experience with functional safety standards (ISO26262, FMEDA)
Förmåner
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP (Purchase Synopsys common stock at a 15% discount)
- Retirement Plans
- Competitive salaries
#ASIC#Design Verification#Principal Engineer#Hsinchu#Taiwan#Engineering#Semiconductor
Företag
Synopsys Inc
Publicerade jobb
för 3 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Ledning
Platser
Hsinchu, Taiwan
Kvalifikation
Kandidatexamen, Masterexamen
Sökande
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