Applications Engineering, Sr Engineer
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling
I korthet
This Sr. Engineer role in Applications Engineering involves leading VCS simulation deployments at customer sites, diagnosing complex issues, and resolving adoption blockers. The position requires strong technical expertise in digital design verification, scripting, and customer-facing problem-solving, with the goal of enabling customer tapeouts and shaping product roadmaps.
Ansvarsområden
- Lead VCS simulation deployments at customer sites, working directly with design and verification teams to integrate the tool into their existing flows and resolve adoption blockers.
- Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related debugging infrastructure.
- Partner with field application engineers and R&D to translate customer pain points into actionable product requirements and validate fixes in real customer environments.
- Drive competitive evaluations and benchmarking engagements, demonstrating VCS capabilities and building the technical case for adoption.
- Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows, improve simulation throughput, and reduce manual intervention.
- Interface with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability based on field feedback.
- Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.
Krav
- Bachelor's in Electronics or Computer Engineering with 5+ years of experience, or Master's with 3+ years, focused on digital design verification.
- Deep hands-on experience with simulation technologies, including VCS or equivalent commercial simulators, and strong understanding of event-driven simulation internals.
- Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL, with the ability to read and debug complex testbenches and RTL.
- Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
- Strong scripting skills in Perl, TCL, Shell, and Make, with the ability to automate workflows and build tooling that improves engineer productivity.
- Working knowledge of UNIX/Linux environments, version control systems, and large-scale verification infrastructure.
Önskade kvalifikationer
- Experience with Synopsys tools like Verdi, exposure to low-power simulation, gate-level verification, and functional safety methodologies is a strong plus.
Förmåner
- Comprehensive range of health, wellness, and financial benefits.
- Total rewards include both monetary and non-monetary offerings.
- May be eligible for an annual bonus, equity, and other discretionary bonuses.
- Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
#VCS#simulation#verification#debug#RTL#UVM#SVA#Verilog#VHDL#Perl#TCL#Shell#Make#UNIX#Linux#version control#low-power simulation#gate-level verification#functional safety
Företag
Synopsys Inc
Publicerade jobb
för 2 veckor sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Sunnyvale, United States
Kvalifikation
Kandidatexamen, Masterexamen
Sökande
Ansök tidigt