Application Engineer-Staff Engineer-18351
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Webbutveckling
I korthet
Synopsys is seeking a Staff Application Engineer in Austin, Texas, to support customers with Interface IP integration and technical issue resolution. This role requires a Bachelor's or Master's degree in Electrical Engineering, 5+ years of experience in ASIC SOC design, and proficiency in Verilog/System Verilog and high-speed protocols.
Ansvarsområden
- Supporting Interface IP customers with integration across the SoC design flow
- Assisting with technical issue resolution and integration reviews
- Helping with silicon and system bring-up, including debugging critical issues
- Collaborating with internal teams to deliver solutions aligned to customer requirements
- Staying current with industry standards, protocol developments, and application trends
- Traveling occasionally to support customer engagements
Krav
- Bachelor’s or Master’s degree in Electrical Engineering or a related field, with a focus on ASIC SOC design
- 5+ years of experience in design, verification, or application engineering
- Proficiency in RTL coding with Verilog and/or System Verilog
- Experience with high-speed protocols such as PCIe, Ethernet and DDR
- Hands-on experience with simulation, synthesis, and static timing analysis (STA)
- Familiarity with UNIX environments and ASIC/SoC tape-out flows
- Knowledge of CDC, RDC, lint, and DFT is a plus
- Curious, results-oriented, and able to manage multiple priorities
- Strong in verbal and written communication in English
- Effective at collaborating across teams
- Analytical, thoughtful, and strong at solving technical problems
- Willing to travel occasionally as needed
Förmåner
- Comprehensive range of health, wellness, and financial benefits
- Details will be provided during the hiring process
- Annual bonus, equity, and other discretionary bonuses
- Competitive total rewards package
#Engineering#ASIC SOC#high-speed protocols#simulation#synthesis#static timing analysis