Analog Design - Staff Engineer
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling
I korthet
Ansvarsområden
- Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators.
- Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications.
- Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes.
- Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune analog circuits in real time.
- Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions.
- Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products.
- Own the full lifecycle of blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD.
Krav
- PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain.
- Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips.
- Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators.
- Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies.
- Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging.
- Working knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued.
Önskade kvalifikationer
- Familiarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus.
- Ability to translate a specification document into a circuit architecture without waiting for a reference design.
- Ability to catch layout issues early, reviewing floorplans and flagging potential performance degradation.
- Comfortable presenting technical data to peers and customers.
- Ability to push back on illogical requirements or gaps in verification plans.
- Ability to work well across teams, coordinating with digital designers, layout engineers, and characterization engineers.
- Keenness to stay current on process technology and circuit techniques.
Förmåner
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement Plans.
- Competitive salaries.
Färdigheter
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Företag
Synopsys IncPublicerade jobb
för 3 veckor sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Mellannivå
Platser
Bengaluru, India
Kvalifikation
Sökande
Ansök tidigt
