The Job

Analog Design, Engineer

Bygg, teknik och hantverk · Bygg- och industriteknik · Elektroteknik

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I korthet

Synopsys is hiring an Analog Design Engineer in Ottawa, Ontario, Canada to design and develop analog building blocks for SERDES, DDR, and memory IP. This role requires hands-on experience with analog circuit design, simulation tools, and an understanding of reliability and layout effects, with minimal supervision.

Ansvarsområden

  • Design and develop analog building blocks for SERDES, DDR, and memory IP, including PLLs, bandgaps, regulators, comparators, and bias circuits.
  • Run simulations across process, voltage, and temperature corners to verify performance, reliability, and margin against spec.
  • Identify and refine circuit topologies to hit power, area, and performance targets without compromising robustness.
  • Work directly with layout engineers to ensure designs account for matching, proximity effects, electromigration, IR drop, and aging.
  • Conduct design reviews with senior engineers and product teams, defending your choices and incorporating feedback.
  • Contribute to design methodology improvements, whether that's updating simulation flows, refining checklists, or documenting lessons learned from previous tapeouts.

Krav

  • Bachelor's or Master's in Electrical Engineering or related field with a strong foundation in analog circuit design.
  • Hands-on experience designing analog circuits for SERDES, DDR, memory, or similar high-speed or mixed-signal applications.
  • Proficiency with industry-standard CAD tools for schematic capture, simulation, and corner analysis, tools like Cadence Virtuoso, HSPICE, or Spectre.
  • Solid understanding of design for reliability including electromigration, IR drop, aging effects, and how they constrain circuit choices.
  • Knowledge of layout effects such as matching requirements, proximity effects, and parasitic extraction, with experience collaborating closely with layout engineers or doing layout yourself.

Önskade kvalifikationer

  • Experience with FinFET or Gate-All-Around process technologies is a plus.
  • Strong problem-solving skills and the ability to debug circuits that don't behave as expected, whether that's a simulation issue, a layout problem, or a fundamental design flaw.
  • Ability to explain circuit topology choices clearly and defend them in design reviews.
  • Skill in managing multiple design tasks concurrently while tracking corner cases, margin checks, and documentation.
  • Proactive approach to identifying necessary simulations and adjustments based on failure modes.
  • Treats layout engineers as design partners and understands the importance of layout quality.
  • Comfortable working independently but knows when to seek help or escalate risks.
  • Stays current with new process nodes, design techniques, and reliability challenges.

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • ETO and FTO Programs (Time Away).
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Retirement Plans.
  • Competitive salaries.
#analog design#serdes#ddr#memory ip#plls#bandgaps#regulators#comparators#bias circuits#simulation#verification#layout#reliability#cad tools#cadence virtuoso#hspice#spectre#finfet#gate-all-around
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Företag

Synopsys Inc

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Mellannivå

Platser

Ottawa, Canada

Kvalifikation

Kandidatexamen, Masterexamen

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