Verification Engineer, Senior

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is looking for a Senior Verification Engineer to join their HSI Digital Design Verification team, focusing on SerDes technology for AI data centers. The role involves developing verification plans, creating testbenches with SystemVerilog and UVM, and debugging simulations. This position offers an opportunity to work on advanced connectivity solutions and contribute to shaping future technology.

Responsibilities

Review digital design specifications and devise verification plans for design functionality.
Understand design implementation and develop testbenches and test cases using SystemVerilog and UVM.
Debug and bring up simulations by identifying root causes.
Integrate analog behavioral models into verification environments to validate digital and analog mixed signal designs and their interactions.
Collaborate with Design, Systems, Firmware, and Analog teams to resolve issues and achieve verification closure.
Facilitate bit-matching between RTL designs and MATLAB system models.
Integrate third-party VIPs for compliance testing of standard protocols such as Ethernet and PCIe.
Take an active role in post-silicon chip bringup to help ensure a smooth transition to working silicon.
Contribute to continuous improvement by developing forward looking automation and solutions.
Enhance verification methodologies, processes, and infrastructure to improve scalability, productivity, and maintainability.
Take opportunities to lead, plan, and coordinate tasks with team members.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Proficiency in SystemVerilog and UVM, including developing and maintaining verification environments and testbenches.
Experience applying constrained random verification methodologies to achieve thorough functional coverage.
Possess strong written and verbal communication skills and convey complex technical ideas clearly.
Detail oriented and able to plan, prioritize, and manage multiple tasks effectively.
Demonstrate a self motivated approach to problem solving and debugging issues.
Comfortable taking ownership of projects and driving them to completion.
Learn quickly and adapt well to evolving technologies and new challenges.
Enjoy collaborating with peers and contributing to a team oriented work environment.

Desired Qualifications

Experience verifying SerDes PHYs, DSPs, or analog mixed signal designs is preferred but not required.
Knowledge in Ethernet and PCIe standards is desirable.
Exposure to formal verification, gate level simulation, and power aware UPF verification techniques.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Opportunity to work on meaningful projects.
Develop advanced technical skills.
Take on significant responsibilities.
Contribute to technology that shapes the future.

Skills

SystemVerilogUVMPythonPerlC/C++GNU MakeMATLABEthernetPCIe

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