Staff SOC Mixed Signal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm Technologies, Inc. is seeking a Staff SOC Mixed Signal Engineer in San Diego, CA. This role involves leading and implementing complex physical design, timing analysis, and power analysis for ASICs and IP cores using advanced tools and deep sub-micron technologies. The position requires a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, and two years of related experience.
Responsibilities
- Leads, plans, and implements designs based on ambiguous or conflicting requirements.
- Executes advanced architecture and implementation of design in the physical design environment using tools like Cadence Innovus and Synopsis PTSI.
- Develops an implementation strategy that meets system requirements and customer needs.
- Resolves complex implementation challenges, design, or verification problems using ASIC engineering practices.
- Owns the design and verification strategies of ASICs and IP cores.
- Reviews strategies and complex IP execution results from junior team members.
- Develops and implements IPs using state-of-the-art tools and deep sub-micron technology nodes (4nm, 3nm).
- Understands and debugs timing specifications with digital designers, facilitating logic changes to improve clock frequency.
- Optimizes clock latencies for major clocks to reduce design ECO cycle time.
- Performs deep analysis of clock and data path timing to identify key issues.
- Runs advanced power checks on multiple blocks and makes recommendations.
- Interprets and reports the results of highly complex performance checks.
- Stays up to date on technical literature and technological advances, suggesting areas for innovation.
- Writes, reviews, and edits technical documentation.
- Maintains regular communication with key team members for alignment.
- Provides technical expertise for design or project reviews and project meetings.
- Acts as a tech lead on projects and owns team deliverables.
- Evaluates team processes for possible improvement.
Requirements
- Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
- Two (2) years of experience in a related occupation.
- Experience with tools/applications like Cadence Innovus, Synopsis PTSI.
- Experience with advanced architecture and implementation of design in the physical design environment.
- Experience with timing, power analysis and physical verification.
- Experience developing and implementing IPs using state-of-the-art tools and deep sub-micron technology nodes (4nm, 3nm).
- Experience with debugging timing specifications and optimizing clock latencies.
- Experience with advanced power checks and interpreting performance check results.
- Ability to write, review, and edit technical documentation.
- Strong contributor at design reviews and project meetings.
- Ability to communicate and implement a development plan.
Desired Qualifications
- Ability to understand and debug timing specifications, facilitate logic changes to improve clock frequency.
- Ability to optimize clock latencies for major clocks to reduce the design ECO cycle time.
- Ability to perform deep analysis of clock and data path timing to identify key issues.
- Ability to interpret the results of highly complex performance checks and report them to team lead.
- Ability to suggest areas for innovation.
- Ability to provide technical expertise for design or project reviews and project meetings.
- Ability to continually evaluate process used in team to facilitate effective work-flow for possible improvement.
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
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