Staff Signal Integrity Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a Staff Signal Integrity Engineer in Bangalore, India. This role involves end-to-end SI/PI architecture, analysis, and signoff for next-generation mobile, compute, and automotive platforms. Requires deep expertise in signal and power integrity with over 12 years of experience.
Responsibilities
- Own end-to-end SI/PI closure for programs (pre-silicon → post-silicon → production)
- Define design targets and layout design guidelines for all high-speed interfaces
- Influence architecture decisions early in product lifecycle
- Ensure SI/PI alignment with product KPIs (performance, yield, power, cost)
- Drive new IP co-design across IC/IO/PHY, package, and PCB
- Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE)
- Influence PDN architecture definition at system and package level, provide related optimum cost solutions
- Partner with SoC/PHY design teams, Package engineering, Board/system teams and OEM/ODM ecosystem
- Lead design reviews and signoff decisions
- Represent SI/PI in program reviews and leadership forums
- Define company-wide SI/PI methodologies
- Drive correlation between pre-silicon models and silicon/lab data
- Lead debug of eye collapse / jitter margin issues, crosstalk and power noise and silicon-package-board interactions
- Drive best practices adoption across programs
- Establish golden methods for system SI/PI
- Mentor senior engineers across SI/PI domains
Requirements
- 12+ years in Signal Integrity / Power Integrity / High-speed systems
- Proven ownership of multiple tapeouts or high-volume products
- Deep expertise in Transmission line theory, EM fundamentals, SI/PI interactions and jitter/noise coupling
- Strong hands-on experience with HFSS, ADS, Sigrity, CST, SIwave, HSPICE tools
- Strong hands-on experience with VNA, TDR, real-time scopes for measurement
- Experience with high-speed interfaces: LPDDR4/5/6, PCIe Gen4/5/6/7, USB4, UFS, 10G–112G+ PHYs, MIPI CSI/DSI
- Experience with System PDN
Desired Qualifications
- Experience with Packaging technologies like FCBGA, 2.5D/3D
- Experience with Products like Data center, Compute and Servers
- Track record of Patents, standards contributions, or published work internal / external conferences
Benefits
- Contribute to next-generation mobile, compute, Automotive and various other connectivity platforms.
- Opportunity to act as System SI/PI owner across full platform (SoC ↔ package ↔ board ↔ connectors ↔ external systems).
- Technical owner for high-speed interfaces and system margins.
- Cross-functional leader driving SIPI driven design convergence.
- Influence architecture decisions early in product lifecycle.
- Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE).
- Drive new IP co-design.
- Mentor senior engineers across SI/PI domains.
#signal integrity#power integrity#hardware engineering#high-speed interfaces#system design#PCB design#package engineering#SoC#automotive#mobile#compute#connectivity#JEDEC#PCI-SIG#MIPI#IEEE