Staff Interface IP Verification Engineer (Pre-Silicon)
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is looking for an experienced Staff Interface IP Verification Engineer to own end-to-end verification of complex Interface IP like PCIe, CXL, DDR, and Ethernet. The role involves architecting and building scalable UVM-based verification environments and driving coverage closure to ensure product quality and reliability for AI accelerators, data centers, and SoCs.
Responsibilities
- Own end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet, from architecture review through signoff and customer release
- Architect and build scalable UVM-based verification environments and reusable verification IP components
- Define verification strategies and detailed test plans by analyzing specifications, identifying protocol corner cases, and mapping coverage goals to real integration risks
- Develop constrained-random, coverage-driven testbenches using SystemVerilog and UVM
- Drive functional coverage closure by analyzing gaps, writing targeted tests, and working with design teams
- Debug complex RTL, protocol, and system-level issues across simulators like VCS or ModelSim
- Mentor verification engineers on UVM methodology, coverage techniques, and debugging approaches
Requirements
- Bachelor's or Master's in Electrical Engineering or Computer Engineering
- At least 5 years of hands-on ASIC or SoC verification experience
- Deep expertise in SystemVerilog and UVM methodologies
- Strong protocol knowledge in one or more of PCIe, CXL, DDR memory interfaces, or Ethernet
- Proven experience developing coverage-driven verification environments and driving coverage closure
- Strong debugging skills across RTL, verification infrastructure, and protocol layers
- Experience using industry-standard simulators such as VCS, ModelSim, Xcelium, or Questa
Desired Qualifications
- Experience with verification IP development, assertion-based verification, or formal methodologies is a strong plus
- Knowledge of modern SoC architectures, high-speed SerDes interfaces, or cache coherency protocols is a plus
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs for time away
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP with a 15% discount on Synopsys common stock
- Retirement Plans
#Hardware Engineering#Semiconductor#ASIC#SoC#Verification
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant