Staff Interface IP Verification Engineer (Pre-Silicon)
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is looking for a Staff Interface IP Verification Engineer to own end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet. You will architect and build scalable UVM-based verification environments and drive functional coverage closure on complex designs through tapeout. This role requires a Bachelor's or Master's in Electrical Engineering or Computer Engineering with at least 5 years of hands-on ASIC or SoC verification experience.
Responsibilities
- Own end-to-end verification of complex Interface IP including PCIe, CXL, DDR, and Ethernet, from architecture review through signoff and customer release
- Architect and build scalable UVM-based verification environments and reusable verification IP components that work across multiple product variants and customer configurations
- Define verification strategies and detailed test plans by analyzing specifications, identifying protocol corner cases, and mapping coverage goals to real integration risks
- Develop constrained-random, coverage-driven testbenches using SystemVerilog and UVM, with a focus on protocol compliance, performance validation, and system-level interaction scenarios
- Drive functional coverage closure by analyzing gaps, writing targeted tests, and working with design teams to ensure all architectural intent is verified before tapeout
- Debug complex RTL, protocol, and system-level issues across simulators like VCS or ModelSim, using waveform analysis, assertions, and protocol monitors to isolate root cause
- Mentor verification engineers on UVM methodology, coverage techniques, and debugging approaches while contributing to verification infrastructure and process improvements across the team
Requirements
- Bachelor's or Master's in Electrical Engineering or Computer Engineering with at least 5 years of hands-on ASIC or SoC verification experience
- Deep expertise in SystemVerilog and UVM methodologies, including building constrained-random testbenches, functional coverage models, and reusable verification components
- Strong protocol knowledge in one or more of PCIe, CXL, DDR memory interfaces, or Ethernet, with demonstrated experience verifying protocol compliance and system-level interactions
- Proven experience developing coverage-driven verification environments and driving coverage closure on complex designs through tapeout
- Strong debugging skills across RTL, verification infrastructure, and protocol layers, with experience using industry-standard simulators such as VCS, ModelSim, Xcelium, or Questa
Desired Qualifications
- Experience with verification IP development, assertion-based verification, or formal methodologies is a strong plus
- Knowledge of modern SoC architectures, high-speed SerDes interfaces, or cache coherency protocols is a plus
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
- Competitive salaries
#Hardware Engineering#Semiconductor#Chip Architecture#Circuit Design#Verification#AI Accelerators#Data Centers#SoCs#ASIC#SoC Verification#Protocol Verification
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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