Staff Digital Verification Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Synopsys is looking for a Staff Digital Verification Engineer to build and evolve SystemVerilog/UVM verification environments for DesignWare IP cores. The role involves defining test plans, writing and debugging testbenches, and collaborating with design teams to ensure the quality and reliability of semiconductor products.

Responsibilities

Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores.
Define comprehensive test plans covering corner cases, protocol compliance, and system-level interactions.
Write and debug complex testbenches, checkers, and assertions for critical PHY blocks and interface logic.
Develop software requirements for the PHY across various configurations and use cases.
Own verification closure for multiple critical blocks within DDR PHYs.
Collaborate with RTL designers, digital architects, and circuit teams.
Manage regression infrastructure and optimize verification cycles.

Requirements

Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering.
4+ years of hands-on verification experience.
Proven track record leading verification teams through IP project delivery.
Strong experience developing SystemVerilog/UVM testbenches from scratch.
Deep expertise writing test plans, implementing checkers, and building assertions.
Proficiency in extracting and interpreting functional and code coverage metrics.
Experience verifying serial interface protocols.
Knowledge of DDR or LPDDR protocols is a strong plus.
Demonstrated ability to own end-to-end verification deliverables.

Desired Qualifications

Experience with AI-assisted verification tools is a plus.
Ability to spot coverage gaps and articulate missing scenarios.
Write assertions that encode real design intent.
Comfortable leading technical discussions with RTL designers and architects.
Manage multiple verification efforts in parallel.
Debug with purpose and systematically move toward root cause.
Treat verification infrastructure as a product.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs for time away.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP to purchase Synopsys common stock at a 15% discount.
Retirement plans.
Competitive salaries.

Skills

SystemVerilogUVMDDRLPDDR

#Digital Verification#Hardware Engineering#Semiconductor#IP Cores#PHY Blocks#Serial Interface Protocols#DDR#LPDDR#SystemVerilog#UVM#Assertions#Coverage Driven Verification#RTL Designers#Architects

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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