Sr Engineer - Physical Design
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Sr Engineer for Physical Design in Hyderabad, India. This role involves owning the physical design implementation of UCIe PHY blocks and testchips on advanced nodes (5nm and below), from floorplanning through tapeout. Responsibilities include driving synthesis, place and route, timing closure, and physical verification using industry-standard tools, while mentoring junior engineers and interfacing with foundry partners.
Responsibilities
- Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes
- Drive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects
- Work directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule
- Lead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers
- Pilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team
- Mentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively
- Interface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions
Requirements
- 2-4 years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification
- Multiple tapeouts and signoffs in 5nm or more advanced process nodes, having taken designs all the way to GDS and dealt with the messiness that comes with it
- Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, knowing the commands, the flow, and the workarounds
- Proven track record working on SoC or IP tapeouts where you owned significant portions of the physical design and were accountable for signoff
- Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale
- Comfortable making tradeoff calls under pressure, like choosing to upsize a cell and take the area hit because you know the timing margin is real and the schedule cannot slip
- Ability to explain a complex physical design issue to an architect or a customer engineer in two sentences without losing the technical nuance that matters
- Experience mentoring junior engineers, taking the time to show them the right way instead of just giving them the answer
- Organized enough to manage three tapeouts at different stages without dropping details, and knowing how to keep stakeholders informed without over-communicating
Desired Qualifications
- Experience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues
- Exposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, we care more about your physical design depth and ability to learn quickly
- You can walk into a timing review with 500 failing paths and know within ten minutes which ones actually matter and which ones are tool artifacts or false paths
- You do not need someone to tell you what to do next; when floorplan is done, you move to placement, when placement converges, you start clock tree, and you flag blockers before they become emergencies
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
- Benefits vary by country and region - check with your recruiter to confirm
#Engineering#Physical Design#Semiconductor#ASIC#5nm#UCIe PHY
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Hyderabad, India
Applicants
Be an early applicant