Sr ASIC Design Verification Engineer - Display
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm Canada ULC is seeking a Sr. ASIC Design Verification Engineer for their Display team in Markham, Ontario. This role involves verifying next-generation Display Processors using industry-leading methodologies and requires strong skills in C++, SystemVerilog, and digital circuit design.
Responsibilities
- Contribute to feature, core and sub-system verification during the design and development phase of next generation ASICs through C/RTL and Gate Level simulations.
- Work closely with the design team to define verification requirements to ensure functional, performance and power correctness.
- Participate in test plan development, execution and verification closure.
- Contribute to creating/maintaining test benches, assertions, and functional coverage models.
- Contribute to implementing flows to automate development processes.
- Participate in debug activities throughout the development cycle.
- Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
- Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.
- Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
- Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
- Writes detailed technical documentation for EDA/IP/ASIC projects.
Requirements
- Strong analytical and debugging skills
- Good working experience with C/C++
- Strong knowledge of Object Oriented Programming (OOP) concepts
- Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC
- Hardware description languages (HDL): Verilog and SystemVerilog
- Strong knowledge of digital circuits and event-driven simulators
- Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
- Strong communication skills (written and verbal) to convey complex information to peers.
- Detailed oriented and be able to plan and prioritize tasks effectively.
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
Desired Qualifications
- Knowledgeable in one or more of the following disciplines is preferred: Display (Pixel processing/composition/compression, MIPI DSI, DisplayPort, HDMI etc.), Bus/interconnect (AHB, AXI)
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
#ASIC#Design Verification#Display Processors#HW Design Verification#C/RTL#Gate Level simulations#Test Benches#Assertions#Functional Coverage#EDA#IP Development#SoC