SOC Verification - Sr. Engineer
In short
Synopsys is looking for a Senior SOC Verification Engineer in Bengaluru, India, to design and develop cutting-edge semiconductor solutions. Responsibilities include building verification test plans, developing SystemVerilog testbenches with UVM, and debugging complex simulation failures. This role requires a Bachelor's or Master's degree and 2-5 years of experience in IP or SOC verification.
Responsibilities
- Build verification test plans from design specs for processor-based SOCs, defining scope, coverage goals, and test scenarios that map to real-world use cases
- Develop and maintain SystemVerilog testbenches and UVM environments, integrating Synopsys VIPs and third-party verification IP for protocols like AXI, USB, PCIe, and MIPI
- Write and analyze SystemVerilog assertions and track code, toggle, and functional coverage to close verification gaps before tapeout
- Debug complex simulation failures across multi-clock-domain SOC designs using VCS, waveform viewers, and scripting to isolate root causes
- Mentor junior verification engineers through design bring-up, testbench architecture decisions, and debugging sessions
- Collaborate with architects, RTL designers, and post-silicon teams to align verification strategy with design intent and silicon validation plans
- Script automation flows using shell, Makefile, and Perl to improve regression efficiency and testbench reusability
Requirements
- Bachelor's or Master's in Electronics Engineering or related field with 2 to 5 years of hands-on experience in IP or SOC verification
- Strong working knowledge of SystemVerilog, UVM, and processor-based SOC verification environments
- Experience with VCS, waveform debugging tools, and integrating third-party VIPs like Synopsys VIP into testbenches
- Solid understanding of AXI and AMBA protocol variants, including how they behave under corner cases and error conditions
- Proficiency in scripting with shell, Makefile, or Perl to automate regression flows and post-process simulation results
- Working knowledge of ASIC design flow, RTL design concepts, and how verification fits into the broader chip development lifecycle
- Experience with ARM core verification, USB, PCIe, or MIPI protocols is a strong plus
Desired Qualifications
- You can take a 200-page design spec, identify the five things most likely to break, and build a verification plan around them without being told what to prioritize
- When a regression fails on a Friday afternoon, you dig into the waveforms and root-cause the issue instead of punting it to Monday
- You explain technical tradeoffs clearly, whether you are talking to a junior engineer who needs guidance or an architect who needs to understand coverage gaps
- You write testbenches and assertions that other engineers can actually read, reuse, and extend six months later
- Leading a small group through a tough debug session feels natural to you, you ask the right questions, keep the team focused, and make sure everyone learns something
- You stay current on verification tools and methodologies because you know the field moves quickly and what worked two years ago might not be the best approach today
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement Plans
- Talented and passionate individuals make a difference
- Comprehensive benefits and rewards
#SOC Verification#Sr. Engineer#Hardware Engineers#semiconductor solutions#chip architecture#circuit design#verification#SystemVerilog#UVM#AXI#USB#PCIe#MIPI#VCS#scripting
Company
Synopsys Inc
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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