SOC Verification - Sr. Engineer
Technology, Data & Digital · Software & Web Development · QA & Testing
In short
Synopsys is seeking a Senior SOC Verification Engineer in Bengaluru, India, to design and verify complex semiconductor solutions. The role involves building verification test plans, developing SystemVerilog testbenches with UVM, integrating VIPs, debugging failures, and mentoring junior engineers. The ideal candidate has 2-5 years of experience in SOC verification with strong knowledge of SystemVerilog, UVM, and AXI/AMBA protocols.
Responsibilities
- Build verification test plans from design specs for processor-based SOCs, defining scope, coverage goals, and test scenarios.
- Develop and maintain SystemVerilog testbenches and UVM environments, integrating Synopsys VIPs and third-party verification IP.
- Write and analyze SystemVerilog assertions and track code, toggle, and functional coverage.
- Debug complex simulation failures across multi-clock-domain SOC designs.
- Mentor junior verification engineers through design bring-up, testbench architecture decisions, and debugging sessions.
- Collaborate with architects, RTL designers, and post-silicon teams.
- Script automation flows using shell, Makefile, and Perl to improve regression efficiency and testbench reusability.
Requirements
- Bachelor's or Master's in Electronics Engineering or related field.
- 2 to 5 years of hands-on experience in IP or SOC verification.
- Strong working knowledge of SystemVerilog, UVM, and processor-based SOC verification environments.
- Experience with VCS, waveform debugging tools, and integrating third-party VIPs.
- Solid understanding of AXI and AMBA protocol variants.
- Proficiency in scripting with shell, Makefile, or Perl.
- Working knowledge of ASIC design flow, RTL design concepts.
Desired Qualifications
- Experience with ARM core verification, USB, PCIe, or MIPI protocols is a strong plus.
- Ability to take a design spec, identify potential issues, and build a verification plan.
- Proactive in debugging and root-causing regression failures.
- Clear communication of technical tradeoffs.
- Ability to write readable, reusable, and extensible testbenches and assertions.
- Natural leadership in guiding debug sessions.
- Staying current on verification tools and methodologies.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP: Purchase Synopsys common stock at a 15% discount.
- Retirement Plans.
- Competitive salaries.
- Work on real customer SOCs, not internal demos.
- Work on complex designs with high stakes.
#SOC#Verification#Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#SystemVerilog#UVM#AXI#USB#PCIe#MIPI#VCS#ASIC Design#RTL Design
Company
Synopsys Inc
Job Posted
3 weeks ago
Expires
in 3 days
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
Be an early applicant