SoC Physical Design

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems. This role focuses on end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving PPA optimization and signoff closure across advanced process nodes.

Responsibilities

Lead end-to-end physical design implementation for large-scale SoCs and complex subsystems, driving projects from architecture definition to successful tapeout.
Own full-chip and subsystem physical design strategy including Floorplanning, Power Planning (PDN), Placement, CTS, Routing, Timing Closure, Signal Integrity, and Physical Verification.
Drive PPA (Performance, Power, Area) optimization and signoff closure across advanced process nodes.
Define and enhance physical design methodologies, automation flows, and best practices to improve design efficiency and quality.
Lead cross-functional collaboration with Architecture, RTL, STA, DFT, Package, CAD, Technology, and Product Engineering teams to achieve aggressive silicon schedules.
Resolve complex design challenges involving timing convergence, congestion, IR/EM, noise, reliability, and manufacturability.
Provide technical leadership during tapeout planning and execution, ensuring high-quality silicon delivery.
Mentor and guide junior engineers, driving technical excellence across the organization.
Influence future design methodologies and contribute to strategic technology roadmap decisions.

Requirements

3+ years of hands-on experience in ASIC/SoC Physical Design with proven success across multiple tapeouts.
Deep expertise in Floorplanning, Power Delivery Networks, Placement, CTS, Routing, Timing Closure, Signal Integrity, IR/EM Analysis, and Physical Verification.
Strong understanding of advanced signoff methodologies including STA, SI, Power Integrity, Reliability, DRC/LVS, ERC, PERC, and ESD verification.
Extensive experience with industry-standard EDA tools such as Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus, Calibre, RedHawk, Voltus, and related signoff tools.
Proven experience leading physical design execution on advanced technology nodes (5nm, 3nm, or equivalent).
Strong expertise in low-power design methodologies, power-aware implementation, and multi-voltage designs.
Demonstrated ability to drive technical decisions, solve complex design challenges, and influence cross-functional teams.
Excellent leadership, communication, and stakeholder management skills.

Desired Qualifications

Experience in high-performance CPU, GPU, AI/ML, Mobile, Networking, Datacenter, or Multimedia SoCs.
Demonstrated ownership of full-chip physical design and successful delivery of complex SoCs to production.
Experience driving methodology development, flow automation, and design productivity improvements.
Prior experience leading and mentoring teams of Physical Design engineers.
Candidates from leading semiconductor product companies are strongly preferred.

Skills

ASIC/SoC Physical DesignFloorplanningPower Delivery NetworksPlacementCTSRoutingTiming ClosureSignal IntegrityIR/EM AnalysisPhysical VerificationSTAPower IntegrityReliabilityDRC/LVSERCPERCESD verificationInnovusICC2/Fusion CompilerPrimeTimeTempusCalibreRedHawkVoltuslow-power design

#SoC Physical Design#Hardware Engineering#ASIC Design#EDA Tools#Tapeout#Advanced Process Nodes#Power Management#Physical Verification#Timing Closure