SoC Infrastructure/NoC, Power & Performance Validation Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm's validation team is looking for a candidate to validate SOC Infrastructure/NoC, Power and Performance in pre-silicon emulation and post-silicon. The role requires an excellent understanding of digital design fundamentals, on-chip interconnects, and analyzing SOC bus architecture, performance, and power. Experience with C, C++, Python, and embedded systems is necessary.

Responsibilities

Validate SOC Infrastructure/NoC, Power and Performance in pre-silicon emulation and post-silicon.
Analyze SOC bus architecture, performance, and power.
Write programs to stress interconnect transactions for appropriate coverage.
Factor in Performance-Power trade-offs.
Debug low level software and hardware issues.
Design and Implement drivers and test content.
Leverage Generative AI technologies for optimizing workflows.

Requirements

Excellent understanding of digital design fundamentals.
Excellent understanding of on-chip interconnects.
SOC Bandwidth, QoS, Latency and Throughput analysis.
Knowledge of Interconnect architectures - NoCs, AXI, AHB.
Solid expertise in various FIFO designs and related performance/functionality aspects.
Knowledge of System Low power modes.
Knowledge of Dynamic clock and voltage scaling operations.
Knowledge of Interrupt architecture.
Knowledge of Debug architecture - interactions with JTAG based debuggers, state dump scripts.
Knowledge of Performance monitor architecture.
Thorough understanding of CPU and DDR concepts, Multimedia, GPU, Peripheral.
Thorough understanding of Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM.
Experience in embedded systems/expertise in C, C++, Python and assembly languages.
Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design.
Familiarity in debug tools including JTAG and kernel debuggers.
Structured program development concepts.
Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation.
Experience leveraging Generative AI technologies for optimizing workflows.
Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC Design, Validation, Verification, or related work experience OR Master's degree in Science, Engineering, or related field and 4+ years of ASIC Design, Validation, Verification, or related work experience OR PhD in Science, Engineering, or related field and 3+ years of ASIC Design, Validation, Verification, or related work experience.
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience OR PhD in Science, Engineering, or related field.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

SOC BandwidthQoSLatencyThroughput analysisInterconnect architecturesAXIAHBFIFO designsSystem Low power modesDynamic clock and voltage scalingInterrupt architectureDebug architectureJTAGPerformance monitor architectureCPUDDRMumtimediaGPUPeripheralMemory hierarchyCachesembedded systemsCC++Pythonassembly languagesDriversStatic powerLeakage powerDynamic powersemiconductor designkernel debuggersGenerative AI

#SoC#Infrastructure#NoC#Power#Performance#Validation#ASIC#Emulation#Post-Silicon