Senior Silicon Engineer, HBM Memory Subsystem Design, Integration and Validation

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

As a Senior Silicon Engineer in Bengaluru, you will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role involves defining microarchitecture, developing RTL, and leading the design, integration, and validation of complex memory controllers and HBM/DDR PHY macros. Requires 10 years of experience in memory subsystem design, integration, or verification, with expertise in DRAM protocols and RTL design flows.

Responsibilities

Define microarchitecture and develop high-quality RTL for memory controller frontends, guiding implementation trade-offs across performance, area, power, timing, and configurability for multi-channel and pseudo-channel configurations.
Lead the design, integration, and delivery of complex memory controller backends and HBM/DDR PHY macros, owning quality closure (DFI pipe wrappers, clock/reset, PLL references, sideband bridging) and schedule from concept to tapeout.
Collaborate with DV teams to build test plans, improve coverage, and validate design intent (UVM, emulation, ECC/RAS error injection), while tracking JEDEC specs and memory conferences for the latest HBM trends.
Lead and support ATE testing, first-silicon lab bring-up, and physical characterization of the HBM PHY and controller across PVT (process, voltage, temperature) corners.
Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, methodology, and systematic root-cause debug.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in memory subsystem design, integration or verification.
Experience with DRAM protocols (HBM2e/HBM3/HBM4 or DDR/LPDDR4x/5/5X) including Joint Electron Device Engineering Council (JEDEC) timing, refresh and training sequences.
Experience with the DFI controller-to-PHY interface, leading a feature or IP block, and mentoring engineers.
Experience in SystemVerilog RTL, simulation and debug flows.

Desired Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience delivering configurable, reusable IP-parameterization, release packaging, integration guides and customer-facing documentation.
Experience integrating third-party controller and PHY IP (Rambus, Cadence/Synopsys class) into production silicon.
Experience with SECDED per pseudo-channel, Reed–Solomon symbol correction, error queues, lane/row repair, address-folded CRC.
Experience with UVM methodology and emulation-based pre-silicon validation, and familiarity with memory telemetry and Silicon Lifecycle Management (SLM) — per-pseudo-channel counters, link availability, continuous eye-opening monitors.

Benefits

Opportunity to drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications.
Develop custom silicon solutions that power the future of Google's TPU.
Contribute to the innovation behind products loved by millions worldwide.
Leverage design and verification expertise to verify complex digital designs.
Collaborate with members of architecture, verification, power and performance, and physical design teams.
Solve technical problems with innovative micro-architecture and practical logic solutions.

Skills

SystemVerilogUVMDDRHBM

#Silicon Engineering#HBM Memory#Subsystem Design#Integration#Validation#AI/ML Hardware#TPU#ASIC#RTL Design#Verification#DRAM#JEDEC#DFI#SystemVerilog#UVM#Emulation#ATE Testing#Silicon Lifecycle Management

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