Senior Logic Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Microsoft is seeking an experienced Senior Logic Design Engineer to join the Compute Silicon & Manufacturing Engineering team. The role involves designing RTL for a high-performance PCIe Subsystem supporting Azure Cobalt, collaborating with cross-functional teams, and ensuring high-quality, on-time delivery of hardware manufacturing solutions.
Responsibilities
- Build a PCIe subsystem composed of multiple IP.
- Collaborate with architecture and IP providers to ensure the subsystem meets SOC requirements.
- Grow micro-architectural knowledge of your own blocks as well as other blocks in the SoC.
- Assess and refine the implementation for area, power, and performance.
- Perform design quality checks such as Synthesis, Lint, CDC, RDC, Low Power Intent, Logic Equivalence.
- Understand Dataflow and Clocking requirements and drive solutions for timing critical paths.
- Automate tasks using scripting for efficiency.
- Provide high-quality functional blocks on schedule and with professional integrity.
- Collaborate with cross-functional team members with respect and a One Microsoft mentality.
- Challenge the status quo with a growth mindset.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience; OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience; OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience; OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Ability to pass Microsoft Cloud Background Check.
- Eligibility to access export-controlled information under relevant regulations.
Desired Qualifications
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- Proficiency with UPF (Low power intent).
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
- Applied understanding of low power design principles.
- Understanding design closure challenges with power and clock domain crossings.
- Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints.
- Organized and detail-oriented.
- Good verbal and written communication skills.
Benefits
- USD $119,800 - $234,700 per year (US national range).
- USD $160,200 - $261,000 per year (San Francisco Bay area and New York City metropolitan area range).
- Potential eligibility for other benefits and compensation.
- Access to a careers page for additional benefits and pay information.
Skills
PCIeAXIAPBPythonTclPerlVCSLintCDCRDCUPFSDC
#Hardware Engineering#Silicon Engineering#RTL#PCIe Subsystem#Azure Cobalt#SOC#Micro-architecture#Area#Power#Performance#Synthesis#Lint#CDC#RDC#Low Power Intent#Logic Equivalence#Dataflow#Clocking#Timing#Scripting#Python#Tcl#Perl#ARM Fabric IPs#IPXACT#Computer Architecture#EDA tools#VCS#VCLP#Spyglass Lint#Questa CDC#Fusion Compiler#Design Compiler#Genus#UPF#Static Timing Analysis#Timing signoff#Low power design#Power and clock domain crossings#Timing constraints#SDC#TCL constraints
About Microsoft
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Company
MicrosoftJob Posted
3 days ago
Employment Type
Full Time
Work mode
Hybrid
Salary
US$119,800–234,700 / year
Experience Level
Senior
Locations
United States
Qualification
Doctoral, Master, Bachelor
Applicants
Be an early applicant
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