The Job

Senior Engineer - DFT

Technology, Data & Digital · Software & Web Development · Software Engineering

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In short

Qualcomm is seeking a Senior Engineer with expertise in ASIC/DFT concepts, scan insertion, ATPG, and coverage analysis. The role involves planning, designing, and testing electronic systems, requiring at least 3 years of relevant experience and strong problem-solving and communication skills.

Responsibilities

  • Plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
  • Collaborate with cross-functional teams to develop solutions and meet performance requirements.
  • Perform ASIC/DFT tasks including scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
  • Define test mode timing constraints and provide timing fixes for violations.
  • Simulate test vectors.
  • Utilize scripting languages such as Perl and shell.
  • Work with equivalence check and DFT DRC rules in RTL lint tools (e.g., Spyglass) and ATPG tools (e.g., Tessent, TK, TetraMax).
  • Potentially work with Genus, Synopsys TetraMax/DFTMax, and Cadence Encounter Test.
  • Work in an international team environment.

Requirements

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • Minimum of 3+ years experience in the area of ASIC/DFT.
  • In-depth knowledge of DFT concepts.
  • In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
  • Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
  • Expertise in scripting languages such as perl, shell, etc.
  • Experience in simulating test vectors.
  • Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax).
  • Excellent communication and team work skills and good English is required.

Desired Qualifications

  • Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus.
  • Ability to work in an international team, dynamic environment.
  • Ability to learn and adapt to new tools and methodologies.
  • Ability to do multi-tasking & work on several high priority designs in parallel.
  • Excellent problem solving skills.

Benefits

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#Hardware Engineering#ASIC#DFT
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Company

Qualcomm

Job Posted

1 week ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

Hyderabad, India

Qualification

Bachelor, Master, Doctoral

Applicants

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