Senior Design Lead
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
HCLTech is seeking a Senior Design Lead with over 5 years of experience in Formal Equivalence Verification (FEV) tools to work on-site in Bangalore, India. Responsibilities include executing FEV, debugging failures, and automating workflows using Python, Perl, or Tcl.
Responsibilities
- Execute RTL ↔ Netlist, Netlist ↔ Netlist, and ECO FEV at block and full-chip levels.
- Debug and resolve non-equivalence failures, aborted points, and compare issues due to synthesis, ECO, scan, and DFT logic.
- Create and maintain reference FEV flows and testcases to validate tool features and methodologies.
- Develop and automate workflows to improve efficiency and runtime of FEV signoff using Python/ Perl/Tcl.
- Work closely with RTL, Synthesis, DFT, and Physical Design teams for issue closure.
- Generate signoff-ready reports and ensure adherence to project signoff criteria.
- Write clear documentation for FEV flows and train users on tool usage and best practices.
Requirements
- 5+ years of experience.
- Experience with Formal Equivalence Verification (FEV) tools is a must.
- Automation using Python/ Perl/Tcl is preferred.
Benefits
- Supercharge your potential.
- Find your career.
- Find your spark.
- A place that knows that helping its customers stay on top starts by putting its people first.
#FEV#design lead#RTL#Netlist#ECO#DFT#Physical Design#Python#Perl#Tcl