Senior Design Lead

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Perform end-to-end physical design flow for advanced nodes (7nm, 5nm, 3nm or below). This role requires 4+ years of experience in floorplanning, power planning, placement, CTS, routing, and post-route optimization, with a focus on achieving timing closure and resolving violations. Collaboration with RTL, DFT, and Foundry teams is key, along with driving methodology improvements and automation.

Responsibilities

Perform end‑to‑end physical design flow: Floorplanning, Power planning (PG grid, IR), Placement & optimization, CTS (Clock Tree Synthesis), Routing, Post‑route optimization.
Achieve timing closure across all modes and corners.
Resolve DRC, LVS, ERC and signoff violations.
Handle low‑power design techniques: Multi‑Vt, Multi‑voltage (UPF), Power gating, clock gating.
Perform physical verification and signoff: STA (Primetime), SI / Crosstalk.
Conduct IR drop & EM analysis.
Work on advanced nodes (7nm, 5nm, 3nm or below).
Collaborate with RTL & Micro‑architecture teams, DFT & Test engineers, Foundry and CAD teams.
Debug complex timing, congestion, power, and variability issues.
Drive methodology improvements and automation (scripts/flows).

Requirements

4+ years of total experience.
Experience in end-to-end physical design flow.
Experience with Floorplanning.
Experience with Power planning (PG grid, IR).
Experience with Placement & optimization.
Experience with CTS (Clock Tree Synthesis).
Experience with Routing.
Experience with Post-route optimization.
Ability to achieve timing closure across all modes and corners.
Ability to resolve DRC, LVS, ERC and signoff violations.
Experience with low-power design techniques: Multi‑Vt, Multi‑voltage (UPF), Power gating, clock gating.
Experience with physical verification and signoff: STA (Primetime), SI / Crosstalk.
Experience with IR drop & EM analysis.
Experience working on advanced nodes (7nm, 5nm, 3nm or below).
Experience debugging complex timing, congestion, power, and variability issues.
Experience driving methodology improvements and automation (scripts/flows).

Desired Qualifications

Ability to collaborate with RTL & Micro‑architecture teams.
Ability to collaborate with DFT & Test engineers.
Ability to collaborate with Foundry and CAD teams.

Benefits

Supercharge your potential.
Find your career.
Find your spark.
A place that knows that helping its customers stay on top starts by putting its people first.
Global technology company.
Home to more than 223,000 people across 60 countries.
Delivering industry-leading capabilities centered around digital, engineering, cloud and AI.
Powered by a broad portfolio of technology services and products.
Work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services.
Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.

Skills

FloorplanningPower planningPlacementCTSRoutingDRCLVSERCLow-power designUPFPower gatingClock gatingPhysical verificationSTAPrimetimeSICrosstalkIR dropEM analysis7nm5nm3nmRTLDFTCADScripting

#Physical Design#VLSI#Semiconductor#Chip Design#EDA

About HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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