R&D Engineering, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Staff Engineer in Sunnyvale, California, to join their R&D Engineering team. This role involves developing and enhancing clock tree synthesis and optimization algorithms for Fusion Compiler, focusing on improving timing closure, power, and design predictability for advanced chips.
Responsibilities
- Develop and enhance clock tree synthesis and clock optimization algorithms in Fusion Compiler, focusing on skew balancing, useful skew, buffering strategies, and insertion delay optimization
- Debug timing and clocking issues in customer designs across advanced process nodes (16nm to 5nm), identify root causes, and translate findings into product improvements
- Design and prototype new CTS and post-CTS optimization flows that integrate into customer methodologies and improve quality of results, runtime, and convergence predictability
- Collaborate directly with R&D engineers, Customer Application Engineers, and Account Consultants to understand real-world design challenges and align product direction with customer needs
- Implement and test new features in C++, Python, and Tcl, ensuring correctness, performance, and maintainability across large, complex codebases
- Analyze clock architecture tradeoffs including skew, latency, OCV-aware optimization, and uncertainty to drive better design outcomes across market verticals
- Contribute to continuous improvement of clock quality of results, addressing power, timing closure, and robustness across evolving process technologies
Requirements
- Master's degree in Computer Science, Computer Engineering, Electronics Engineering, Mathematics, or related field with 2+ years of professional experience, or Ph.D. in a related field
- Strong proficiency in C++ for performance-critical algorithm development and systems software
- Experience with clock tree synthesis, static timing analysis, timing closure, or physical synthesis flows in an EDA or semiconductor design context
- Solid understanding of clock architecture concepts including skew, latency, insertion delay, transition, uncertainty, and OCV-aware optimization
- Familiarity with VLSI processes and physical design methodology, including timing, area, power, congestion, and signal integrity tradeoffs
- Working knowledge of Python and Tcl for scripting, automation, and tool integration
Desired Qualifications
- Experience with advanced technology nodes (16nm to 5nm) is a plus, understanding the unique challenges of finFET and gate-all-around processes strengthens your ability to solve real customer problems
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
- Competitive salaries
- Annual bonus, equity, and other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
Skills
C++PythonTcl
#R&D#Engineering#Staff Engineer#Software#Chip Design#Verification#Manufacturing#AI/ML#GenAI#Cloud#EDA#Clock Networks#Timing Closure#Skew Balancing#Buffering Strategies#Insertion Delay Optimization#Customer Debug#Fusion Compiler#Physical Design#VLSI#FinFET#Gate-All-Around
About Synopsys Inc
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
5 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$138,000–207,000 / year
Experience Level
Senior
Locations
Sunnyvale, United States
Qualification
Master, Doctoral
Applicants
Be an early applicant
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