R&D Engineering, Sr Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is seeking a Senior R&D Engineer in Seongnam-si, South Korea, to develop and optimize Electronic Design Automation (EDA) solutions for advanced chip design and manufacturing. This role involves working with foundry partners, debugging complex physical design issues, and leveraging state-of-the-art technologies like AI/ML and Cloud.

Responsibilities

Develop and optimize foundry implementation and 3DIC solutions using Synopsys Fusion Compiler, aligned with reference methodology and advanced node requirements.
Provide direct engineering support to foundry partners and end customers on DTCO, PPA optimization, and test chip bring-up for cutting-edge process nodes.
Debug complex place and route, timing, power, and physical verification issues across multi-corner, multi-mode designs using tools like PrimeTime, StarRC, IC Validator, and RedHawk.
Drive foundry test chip projects from RTL to GDS, coordinating with Synopsys advanced node enablement teams and foundry process groups.
Work with field account teams and internal jumpstart teams to support mutual customer engagements and accelerate adoption of Synopsys physical design solutions.
Collaborate with cross-functional engineering teams across geographies to resolve real project issues, improve implementation flows, and close PPA gaps.
Explore and integrate productivity improvements using modern engineering tools and AI-assisted solutions like Cursor to accelerate design and debug cycles.

Requirements

Bachelor's or Master's degree in Electrical Engineering with 2+ years of hands-on experience in physical design implementation.
Proficiency in place and route methodology, hierarchical design, and timing signoff using Synopsys Fusion Compiler or equivalent P&R tools.
Hands-on experience with physical design signoff tools such as PrimeTime for timing, StarRC for extraction, IC Validator for DRC/LVS, or RedHawk for power analysis.
Demonstrated ability to debug complex implementation issues across multiple domains including timing closure, power integrity, and physical verification.
Experience working on high-performance or low-power designs with a track record of contributing to PPA improvements and flow optimization.

Desired Qualifications

Real tape-out experience on SoC, CPU, or GPU projects is a strong plus.
Exposure to AI-assisted engineering tools like Cursor or similar automation frameworks is a plus.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement plans that vary by region and country.
Competitive salaries.

Skills

AI/MLGenAICloudFusion CompilerPrimeTimeStarRCIC ValidatorRedHawkCursor

#R&D Engineering#Senior Engineer#EDA#Chip Design#Verification#Manufacturing#AI/ML#GenAI#Cloud#Semiconductors#Physical Design#Place and Route#Timing Closure#Power Integrity#Performance Analysis#Area Optimization#Fusion Compiler#PrimeTime#StarRC#IC Validator#RedHawk#DTCO#3DIC#Test Chip Bring-up#Process Nodes#Customer Engagements#Methodology Development#Automation#Foundry Partners

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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