R&D Engineering, Manager

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is seeking an experienced R&D Engineering Manager to lead a team focused on developing embedded memory IP for advanced FinFET nodes. The role requires deep expertise in memory design, circuit implementation, and team leadership, with a focus on driving innovation in AI, automotive, and high-performance computing sectors.

Responsibilities

Lead a team of engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations across advanced FinFET nodes
Oversee the full memory design flow from architecture definition through schematic entry, simulation, layout planning, verification, characterization, and model generation
Drive low-power and area-efficient circuit design strategies, balancing performance, variation, and manufacturability constraints
Coordinate with CAD teams on layout verification, parasitic extraction, and compiler automation using Perl and Python
Manage project timelines, prioritize deliverables, and resolve technical and resourcing issues across multi-site teams
Build and maintain relationships with internal stakeholders and external customers, translating technical requirements into executable design plans
Mentor engineers on memory compiler development, transistor-level design, and advanced node challenges

Requirements

BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from a recognized institute or university
15+ years of hands-on experience in embedded memory design, including SRAM, Register File, TCAM, or ROM
Deep expertise across the full memory design flow: architecture, circuit design, layout, compiler automation, characterization, timing, and model generation
Proven experience leading engineering teams and delivering complex projects on schedule in a multi-site environment
Strong proficiency in Perl and Python for design automation and scripting
Hands-on experience with deep submicron and FinFET technologies, including variation-aware design techniques
Solid understanding of CMOS fundamentals, digital design, RC circuits, transfer function analysis, and CMOS fabrication processes

Desired Qualifications

Ability to identify and explain timing violation issues and their fixes in layout reviews
Skill in managing multiple projects and shifting priorities while communicating risks and tradeoffs
Ability to build trust across teams through follow-through and acknowledgment
Capability to have difficult conversations about design specifications early to provide options
Mentoring engineers by asking guiding questions
Staying current on memory design trends, advanced node challenges, and industry best practices

Benefits

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement plans that vary by region and country
Competitive salaries

Skills

AI/MLGenAICloudPerlPython

#Engineering#R&D

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

See all open jobs at Synopsys Inc Read more about Synopsys Inc Website